The AES IP core offers an ultracompact implementation of the Rijndael cipher, compliant with the NIST AES encryption standard. Designed to tackle 128-bit data blocks using 128 or 256-bit keys, this core is renowned for its small size of less than 3,000 gates in the base version. It includes key expansion functionality and supports encryption across various modes such as ECB, CBC, OFB, and CTR. With an emphasis on a fully synchronous design, the core facilitates straightforward integration, whether in source or netlist format, for both ASIC and FPGA platforms, offering optional data integrity and power attack resistance features.
