The CVC Verilog Simulator is a state-of-the-art electronic design automation tool that supports comprehensive Verilog HDL simulation. This simulator is particularly noted for its adherence to the IEEE 1364 2005 standard and its ability to compile Verilog directly into native machine instructions for X86_64 systems. By executing as a native Linux binary, it offers unparalleled speed and efficiency in the simulation process.
The CVC simulator is versatile, supporting both compiled and interpreted modes. This flexibility allows for fast elaboration of large designs during the initial phases when using interpreted mode, while compiled mode delivers greater simulation speeds. This is achieved by compiling designs into binaries that execute faster than any other available simulator, removing flow graph and optimization steps to speed up elaboration.
Moreover, the simulator boasts a wide range of features, including built-in toggle coverage, VCD/EVCD/FST design state dump formats, and options for using additional X86 cores for parallel FST generation. It also offers full PLI support, utilizing the fastest vpi_ and no overhead dpi_ interfaces, enhancing integration with C/C++ applications. Fully compliant with the Verilog 1364-2005 standard, CVC is an invaluable tool for those needing detailed and high-speed simulation capabilities.
