IQonIC Works' RISC-V PLIC is designed to handle complex interrupt management tasks in systems with multiple interrupt sources and destinations. Conforming to the RISC-V PLIC specification, the controller is highly configurable to suit the specific needs of various applications. It supports from 31 to 1023 interrupt sources and can manage up to 32 hardware thread (hart) contexts, enabling flexible and efficient interrupt handling across wide-ranging system architectures.
The PLIC ensures secure and efficient allocation of interrupts through configurable priority levels and supports asynchronous and synchronous signal requests, as well as edge-triggered sensitivities. Its interface uses AHB-Lite for priority, enables, and claim completion settings, facilitating streamlined processing and response management.
Designed for integration into both single and multiprocessor environments, the PLIC allows interrupt sharing across different processor execution contexts, thereby optimizing resource utilization. Through this functionality, the PLIC enhances the system's ability to manage a broad spectrum of asynchronous events, vital for high-performance and real-time applications.
