All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
The ARINC 818 Product Suite by Great River Technology provides a comprehensive solution for high-performance digital video transmission in avionics applications. It supports the implementation, qualification, testing, and simulation of ARINC 818 products. This suite allows developers to access essential ARINC 818 tools and resources. It ensures optimal performance and reliability in mission-critical equipment by offering both hardware and software components tailored for the ARINC 818 standard. With its focus on high-speed data transfer and signal integrity, the ARINC 818 Product Suite is ideal for applications requiring lossless video transmission and real-time data handling in challenging conditions.
TTTech's Time-Triggered Ethernet (TTEthernet) is a breakthrough communication technology that combines the reliability of traditional Ethernet with the precision of time-triggered protocols. Designed to meet stringent safety requirements, this IP is fundamental in environments where fail-safe operations are absolute, such as human spaceflight, nuclear facilities, and other high-risk settings. TTEthernet integrates seamlessly with existing Ethernet infrastructure while providing deterministic control over data transmission times, allowing for real-time application support. Its primary advantage lies in supporting triple-redundant networks, which ensures dual fault-tolerance, an essential feature exemplified in its use by NASA's Orion spacecraft. The integrity and precision offered by Time-Triggered Ethernet make it ideal for implementing ECSS Engineering standards in space applications. It not only permits robust redundancy and high bandwidth (exceeding 10 Gbps) but also supports interoperability with various commercial off-the-shelf components, making it a versatile solution for complex network architectures.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Eliyan's NuLink Die-to-Die (D2D) PHY products are designed to provide high-performance, low-power connectivity between chips, or 'chiplets,' in a system. Using standard organic laminate packaging, these IP cores maintain power and performance levels that would traditionally require advanced packaging techniques like silicon interposers. This eliminates the need for such technology, allowing cost-effective system design and reducing thermal, test, and production challenges while maintaining performance. Eliyan’s approach enables flexibility, allowing a broad substrate area that supports more chiplets in the package, significantly boosting performance and power metrics. These D2D PHY cores accommodate various industry standards, including UCIe and BoW, providing configurations tailor-made for optimal bump map layout, thus enhancing overall system efficiency.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
The Multi-Protocol SerDes provided by Silicon Creations serves as an essential component for high-speed data interfaces across multiple industry protocols. This SerDes portfolio accommodates a vast array of protocols such as PCIe, JESD204, XAUI, and many more, facilitating broad compatibility with industry standards. Operating across 12nm to 180nm processes, these interfaces support data rates from 100 Mbps to an impressive 32.75 Gbps. Incorporating advanced features like programmable de-serialization widths and adaptive equalization, the Multi-Protocol SerDes ensures optimal signal integrity and performance even in demanding environments. The design includes jitter cleaner functions and employs low-latency optimized PMAs, delivering high precision and speed across various operational scenarios. This comprehensive adaptability ensures seamless integration into a wide range of applications from communications to high-performance computing. Supported by robust architectures, the SerDes enables enhanced efficiency and reliability, featuring low power consumption and reduced area overheads. With a commitment to customer satisfaction, Silicon Creations offers complete solutions through partnerships with leading controller vendors, cementing its products as high-value choices for modern electronic systems.
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The HOTLink II Product Suite by Great River Technology is tailored for mission-critical avionics systems requiring robust data communication. It enables seamless data transfer and ensures consistent performance under high-stress operational environments. This suite incorporates advanced technologies to handle complex data streams effectively. It includes component options that enhance data throughput and communication efficiency, meeting stringent industry standards for avionics platforms. Designed with precision, the HOTLink II suite supports the integration and management of large datasets, ensuring that avionics systems can perform efficiently and reliably, crucial for modern aircraft and defense applications.
The Chipchain C100 is a pioneering solution in IoT applications, providing a highly integrated single-chip design that focuses on low power consumption without compromising performance. Its design incorporates a powerful 32-bit RISC-V CPU which can reach speeds up to 1.5GHz. This processing power ensures efficient and capable computing for diverse IoT applications. This chip stands out with its comprehensive integrated features including embedded RAM and ROM, making it efficient in both processing and computing tasks. Additionally, the C100 comes with integrated Wi-Fi and multiple interfaces for transmission, broadening its application potential significantly. Other notable features of the C100 include an ADC, LDO, and a temperature sensor, enabling it to handle a wide array of IoT tasks more seamlessly. With considerations for security and stability, the Chipchain C100 facilitates easier and faster development in IoT applications, proving itself as a versatile component in smart devices like security systems, home automation products, and wearable technology.
The Time-Triggered Protocol (TTP) designed by TTTech is an advanced communication protocol meant to enhance the reliability of data transmission in critical systems. Developed in compliance with the SAE AS6003 standard, this protocol is ideally suited for environments requiring synchronized operations, such as aeronautics and high-stakes energy sectors. TTP allows for precise scheduling of communication tasks, creating a deterministic communication environment where the timing of data exchanges is predictable and stable. This predictability is crucial in eliminating delays and minimizing data loss in safety-critical applications. The protocol lays the groundwork for robust telecom infrastructures in airplanes and offers a high level of system redundancy and fault tolerance. TTTech’s TTP IP core is integral to their TTP-Controller ASICs and is designed to comply with stringent integrity and safety requirements, including those outlined in RTCA DO-254 / EUROCAE ED-80. The versatility of TTP allows it to be implemented across varying FPGA platforms, broadening its applicability to a wide range of safety-critical industrial systems.
The DisplayPort 1.4 IP-core offered by Parretto B.V. is a compact yet potent solution for DisplayPort connectivity needs. Supporting a range of link rates from 1.62 to 8.1 Gbps, this IP-core accommodates varied setups with ease, including embedded DisplayPort (eDP) applications. It provides support for multiple lane configurations and both native video and AXI stream interfaces. The inclusion of Single and Multi Stream transport modes enhances its versatility for different video applications. Tailored for modern FPGA devices, the core supports a comprehensive video format range, including RGB and various YCbCr colorspaces. A standout feature is the secondary data packet interface, enabling audio and metadata transport alongside video signals. This makes it a full-fledged solution for video-centric applications, complemented by a Video Toolbox geared for video processing tasks like timing and test pattern generation. Parretto ensures the IP-core's adaptability by offering it with a thin host driver and API for seamless integration. The core is compatible with an extensive list of FPGA devices, such as AMD UltraScale+ and Intel Arria 10 GX. Customers benefit from the availability of source code via GitHub, promoting easier customization and deep integration into diverse systems. Comprehensive documentation supports the IP-core, ensuring efficient setup and utilization.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
The RISCV SoC developed by Dyumnin Semiconductors is engineered with a 64-bit quad-core server-class RISCV CPU, aiming to bridge various application needs with an integrated, holistic system design. Each subsystem of this SoC, from AI/ML capabilities to automotive and multimedia functionalities, is constructed to deliver optimal performance and streamlined operations. Designed as a reference model, this SoC enables quick adaptation and deployment, significantly reducing the time-to-market for clients. The AI Accelerator subsystem enhances AI operations with its collaboration of a custom central processing unit, intertwined with a specialized tensor flow unit. In the multimedia domain, the SoC boasts integration capabilities for HDMI, Display Port, MIPI, and other advanced graphic and audio technologies, ensuring versatile application across various multimedia requirements. Memory handling is another strength of this SoC, with support for protocols ranging from DDR and MMC to more advanced interfaces like ONFI and SD/SDIO, ensuring seamless connectivity with a wide array of memory modules. Moreover, the communication subsystem encompasses a broad spectrum of connectivity protocols, including PCIe, Ethernet, USB, and SPI, crafting an all-rounded solution for modern communication challenges. The automotive subsystem, offering CAN and CAN-FD protocols, further extends its utility into automotive connectivity.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The High-Speed Interface Technology by VeriSyno Microelectronics Co., Ltd. encompasses a range of connectivity solutions designed to meet the rigorous demands of modern applications. This suite includes versatile interfaces such as USB, DDR, MIPI, HDMI, PCIe, and SATA, each meticulously crafted to ensure seamless data transmission and robust performance across various technological landscapes. VeriSyno's high-speed interface solutions are built upon a robust framework that supports rigorous signaling protocols, ensuring consistency and reliability in high-bandwidth environments. These interfaces are optimized for diverse manufacturing processes, ranging from 28nm to 90nm, demonstrating flexibility and adaptability to next-generation design requirements. The technology facilitates customization, allowing clients to tailor interface attributes to specific application needs, thereby maximizing system efficiency. With a commitment to excellence, VeriSyno consistently updates its technology suite to incorporate latest advancements, ensuring clients benefit from leading-edge connectivity solutions.
Ventana's System IP is a critical component for next-generation RISC-V platforms, providing essential support for integrating high-performance CPUs into sophisticated computing architectures. This IP block enables system-level functionality that aligns with the stringent demands of modern computing environments, from cloud infrastructures to advanced automotive systems. Equipped with comprehensive system management capabilities, the System IP includes crucial components such as memory management units and I/O handling protocols that enhance the overall efficiency and reliability of RISC-V-based systems. It is optimized for virtualization and robust security, essential for maintaining integrity in high-traffic data centers. The System IP supports seamless integration with Ventana's Veyron processor families, ensuring scalability and consistent performance under demanding workloads. Its design allows for easy customization, making it an ideal choice for companies looking to innovate and expand within the rapidly evolving field of high-performance computing.
The Hyperspectral Imaging System offers advanced solutions for capturing detailed spectral information beyond the visible range. This system provides unmatched access to spectral imaging, making it ideal for applications requiring precise detail, such as environmental monitoring and industrial inspection. Hyperspectral imaging divides the spectrum into many bands, delivering a richer data set that enhances material identification, classification, and analysis. This technology is pivotal where high precision in spectral analysis is necessary, aiding sectors such as agriculture and defense. Capable of capturing spectral data in high resolution across multiple wavelengths, the system's applications extend to medical fields, offering improved diagnostics and insights into biological samples. Integrating state-of-the-art CMOS technology, it ensures fast, accurate data acquisition with lower power consumption.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
Silicon Creations' Bi-Directional LVDS Interfaces are engineered to offer high-speed data transmission with exceptional signal integrity. These interfaces are designed to complement FPGA-to-ASIC conversions and include broad compatibility with industry standards like FPD-Link and Camera-Link. Operating efficiently over processes from 90nm to 12nm, the LVDS interfaces achieve data rates exceeding 3Gbps using advanced phase alignment techniques. A standout feature of this IP is its capability to handle independent LVCMOS input and output functions while maintaining high compatibility with TIA/EIA644A standards. The bi-directional nature allows for seamless data flow in chip-to-chip communications, essential for modern integrated circuits requiring high data throughput. The design is further refined with trimmable on-die termination, enhancing signal integrity during operations. The LVDS interfaces are versatile and highly programmable, meeting bespoke application needs with ease. The interfaces ensure robust error rate performance across varying phase selections, making them ideal for video data applications, controllers, and other high-speed data interfaces where reliability and performance are paramount.
The BlueLynx Chiplet Interconnect system provides an advanced die-to-die connectivity solution designed to meet the demanding needs of diverse packaging configurations. This interconnect solution stands out for its compliance with recognized industry standards like UCIe and BoW, while offering unparalleled customization to fit specific applications and workloads. By enabling seamless connection to on-die buses and Networks-on-Chip (NoCs) through standards such as AMBA, AXI, ACE, and CHI, BlueLynx facilitates faster and cost-effective integration processes. The BlueLynx system is distinguished by its adaptive architecture that maximizes silicon utilization, ensuring high bandwidth along with low latency and power efficiency. Designed for scalability, the system supports a remarkable range of data rates from 2 to 40+ Gb/s, with an impressive bandwidth density of 15+ Tbps/mm. It also provides support for multiple serialization and deserialization ratios, ensuring flexibility for various packaging methods, from 2D to 3D applications. Compatible with numerous process nodes, including today’s most advanced nodes like 3nm and 4nm, BlueLynx offers a progressive pathway for chiplet designers aiming to streamline transitions from traditional SoCs to advanced chiplet architectures.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
In smartphone applications, ActLight’s Dynamic PhotoDetector (DPD) offers a step-change in photodetection technology, enhancing features such as proximity sensing and ambient light detection. This high sensitivity sensor, with its ability to detect subtle changes in light, supports functions like automatic screen brightness adjustments and energy-efficient proximity sensing. Designed for low voltage operation, the DPD effectively reduces power consumption, making it suitable for high-performance phones without increasing thermal load. The technology also facilitates innovative applications like 3D imaging and eye-tracking, adding richness to user experiences in gaming and augmented reality.
The Camera PHY Interface for Advanced Processes from Curious Corporation is engineered to support advanced imaging needs, optimizing data transfer in demanding environments. This interface excels in high-speed performance, providing robust connectivity for complex camera configurations. It is particularly valuable in applications requiring efficient bandwidth utilization and superior image data handling. Designed with modern imaging demands in mind, the Camera PHY Interface offers compatibility with various camera modules, allowing for seamless integration into diverse systems. Engineers can utilize this interface to enhance image capture capabilities, making it ideal for high-definition multimedia applications. Furthermore, its adaptability to different process nodes ensures that it can meet the rigorous demands of modern technological innovations. The interface's ability to support high-frequency operation while minimizing power consumption makes it suitable for portable and fixed imaging solutions.
The MIPI solutions offered are comprehensive design and verification intellectual properties, continually updated to align with the latest specifications while maintaining backward compatibility. They cover an extensive range of standards such as CSI-2, DSI, UNIPRO, I3C, RFFE, Soundwire, BIF, and SPMI. These solutions are critical for high-speed interfaces required in mobile and automotive devices, ensuring robust performance across various applications.\n\nMIPI CSI-2 solutions, for example, support transmitter functionalities for Combo C/DPHY and receiver capabilities, offering complete solutions from version 1.0 through to 3.0. Each specification version builds on the last, ensuring that users can maintain compatibility with older systems while accessing cutting-edge features. DSI and DSI-2 offer similar comprehensive support, providing critical tools for display interfacing.\n\nOn top of this, auxiliary standards like I3C, RFFE, and Soundwire reinforce PRSsemicon's capacity to equip the latest devices with advanced communication capabilities. Their design includes master and slave functionality, ensuring comprehensive inter-device compatibility and communication efficiency. The continuous advancements in these IPs make them integral for any semiconductor-driven market, especially in technologically dynamic fields like automotive and consumer electronics.
Analog Bits provides robust I/O solutions that are essential for the efficient transfer of signals between semiconductor devices and their external environment. These input/output interfaces are designed to meet the most demanding performance criteria, ensuring fast data rates and minimal signal distortion. Their I/O IP solutions can accommodate a variety of protocols, including high-speed digital interfaces and analog conversions, offering versatility and support for applications such as networking, data processing, and consumer electronics. By optimizing the signal integrity and electromagnetic compatibility, these I/Os enhance the overall system performance. Equipped with advanced features for low power consumption, these I/Os contribute to reducing the overall energy footprint of semiconductor devices, making them ideal for battery-operated devices and environmentally sensitive applications. Analog Bits' I/Os are comprehensively integrated to function seamlessly within mixed-signal environments, further broadening their application range.
Matterhorn USB4 Retimer stands as an advanced engineering marvel, redefining the data transfer potential of USB4 technologies. This retimer allows for optimized data transfer rates, pushing the boundaries set by new-gen USB4 specifications. As technology rapidly evolves, the Matterhorn positions itself as a versatile component, capable of enhancing everyday consumer laptops and devices into high-performance units fit for gaming. Key to its operation is Matterhorn's ability to manage power effectively, maintaining low active power consumption and reducing the bill of materials cost. It achieves full USB4 compliance, ensuring devices can achieve top speeds while retaining backward compatibility with older USB standards like USB 3.2. This ensures it meets the diverse demands of end-users, enhancing the performance of a wide array of peripherals. Matterhorn's design is compact, maximizing maneuverability in system assembly with packages up to 50% smaller than competing products. As a plug-and-play solution, it requires minimal tuning, offering seamless integration into systems that demand high-speed data transactions. The embedded diagnostics tools further add to its usability, providing real-time insights into the retimer's performance and health, making it a top choice for achieving high data integrity in complex designs.
Naneng Microelectronics offers a versatile Universal High-Speed SERDES capable of operating in a broad range of speeds from 1Gbps to 12.5Gbps. This SERDES is engineered to provide seamless and agile data transmission, underpinning critical communications infrastructure in various applications. The high-speed capabilities of this serializer/deserializer underline its suitability for high-performance networking solutions. Its flexible deployment options make it an ideal candidate for integration in a variety of system architectures, promoting a balance between speed and signal integrity. The design includes robust features to counter signal degradation and maintain the integrity of transmitted data, ensuring reliable operation across extensive data networks. Support for high data rates ensures this SERDES component meets and exceeds industry standards, delivering enhanced data throughput and supporting next-generation electronic systems. With adaptability at its core, the Universal High-Speed SERDES exemplifies comprehensive technological solutions in the semiconductor industry.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The JESD204B Multi-Channel PHY from Naneng Microelectronics is designed to meet the rigorous demands of high-speed data transmission. Featuring a data rate capability of up to 12.5Gbps, this physical layer multi-channel interface supports a wide array of applications requiring reliable and efficient data transfer. Its versatile architecture ensures seamless integration into complex systems, providing robust performance benefits in the field of data communications. A comprehensive design enhances usability and flexibility, allowing customization for specific industrial needs. This PHY is particularly adept in high-density environments, ensuring precision synchronization across multiple channels, critical for signal integrity in today's intricate electronic ecosystems. Furthermore, the solution's efficient layout allows for ease of interoperability with existing infrastructure, reducing integration costs and time-to-market for end-users. This makes the JESD204B Multi-Channel PHY an attractive choice for enterprises aiming for optimal performance in digital communication systems without compromising efficiency.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The MIPITM SVRPlus2500 provides an efficient solution for high-speed 4-lane video reception. It's compliant with CSI2 rev 2.0 and DPHY rev 1.2 standards, designed to facilitate easy timing closure with a low clock rating. This receiver supports PRBS, boasts calibration capabilities, and offers a versatile output of 4/8/16 pixels per clock. It features 16 virtual channels and 1:16 input deserializers per lane, handling data rates up to 10Gbps, making it ideal for complex video processing tasks.
The MIPITM SVTPlus-8L-F is a cutting-edge serial video transmitter designed for FPGAs. This transmitter adheres to CSI2 rev 2.0 and DPHY rev 1.2, featuring 8 lanes and capable of handling data rates of up to 12Gbps. It's engineered for high-performance video applications, boasting robust processing capabilities. Its support for advanced transmission protocols ensures seamless integration and compatibility with a wide range of video systems.
Specialized for advanced radio frequency applications, the RF-SOI and RF-CMOS platform merges high-performance substrates with CMOS design flexibility to enable sophisticated wireless communication solutions. SOI (Silicon-On-Insulator) technology in this platform excels in reducing parasitic capacitance, thereby enhancing speed and power efficiency – critical for RF applications where performance must meet stringent wireless standards. This platform offers extensive frequency range support, from sub-GHz to millimeter wave frequencies, making it a suitable choice for cellular infrastructure, IoT devices, and automotive radar systems. By integrating RF-SOI, the solutions achieve low-loss and high linearity, addressing the demands of next-generation wireless networks. The additional benefit of leveraging RF-CMOS provides improved integration capabilities for multi-function devices on a single chip. Tower Semiconductor's platform is augmented by its comprehensive design enablement resources, including standard cell libraries and PDKs, to facilitate efficient design cycles. The enhanced capabilities of the RF-SOI and RF-CMOS platform thus continue to push forward the frontier of wireless technology, supporting the evolution of high-speed data communications.
Silicon Library's MIPI IP encompasses robust support for both MIPI D-PHY transmitters and receivers, playing a pivotal role in the high-speed transmission of camera and display data. Designed for integration into a variety of mobile and embedded applications, it ensures efficient data pathways for smartphones, tablets, and other IoT devices. The MIPI IP is essential for facilitating high-speed data transfer with low power consumption, making it ideal for modern portable devices that demand extended battery life. It offers support for dynamic range and multi-lane configurations, providing flexibility and scalability for manufacturers integrating it into diverse designs. Engineered for compliance with MIPI specifications, this IP module enhances device interoperability and scaling capabilities. The integration of MIPI IP supports the seamless transfer of high-quality images and video, contributing significantly to the advanced functionalities of cameras and displays while maintaining low latency and high data integrity.
The 1394b PHY IP Core provides a robust, hardware-level implementation for AS5643 PHY layer applications, ideal for avionics communications. It offers a standardized PHY-Link interface, ensuring compatibility and seamless integration with high-speed data transfer systems. Built to manage sophisticated data connectivity tasks, this core supports high-performance operations needed for complex networking environments. Its implementation within systems enhances data reliability and offers significant enhancements in data integrity across all connected components. Designed with an emphasis on operational efficiency, the 1394b PHY IP Core detaches the complexities associated with data communications, allowing for improved system functionality and performance. Whether for current operational needs or future expansions, this core provides a strategic advantage in maintaining rigorous communication protocols.
With an emphasis on performance, the MIPITM SVTPlus2500 is a robust 4-lane video transmitter adhering to CSI2 rev 2.0 and DPHY rev 1.2 standards. It facilitates timing closure with its low clock rating and supports PRBS for precise data management. The transmitter can handle 8/16 pixel inputs per clock and offers programmable timing parameters. Equipped with 16 virtual channels, this IP is engineered for high-speed video transmission.
The Glasswing Ultra-Short Reach SerDes is a cutting-edge interconnect solution leveraging the unique CNRZ-5 Chord Signaling technology. It is designed to enhance high-bandwidth and low-power performance across chip-to-chip interfaces, optimizing silicon use by lowering pin count while boosting throughput. This innovative technology transmits five bits over six wires, effectively doubling bandwidth and minimizing power requirements. This solution allows the seamless creation of a chiplet ecosystem, facilitating complex connections in high-performance computing environments. Notably, Glasswing delivers significantly higher throughput per pin, alongside lower power consumption compared to traditional NRZ solutions. This feature makes it particularly valuable for applications such as AI, ML, networking, and high-performance computing, where efficiency and throughput are critical. Glasswing excels in modularity and diagnostics, offering dynamic configuration and real-time signal strength monitoring. Its capabilities allow integration into large multi-chip modules with high signal integrity, unlocking potential in fields ranging from satellite communications to consumer electronics. Furthermore, the use of substrate rather than complex silicon interposers reduces cost and complexity, making it a financially attractive option for large-scale projects.
StreamDSP's MIPI Video Processing Pipeline is crafted for seamless integration into advanced embedded systems, offering a turnkey solution for video handling and processing. It supports the MIPI CSI-2 and DSI-2 standards, allowing it to process various video formats and resolutions efficiently, including ultra-high-definition video. The architecture is designed to work with or without frame buffering, depending on latency needs, enabling system designers to tailor performance to specific application requirements. This flexibility ensures that StreamDSP's video pipeline can handle the demands of cutting-edge video applications like real-time video analysis and broadcast video streaming, while maintaining optimal resource usage.
Time-Sensitive Networking (TSN) from TTTech represents a significant advancement in industrial communication, offering precise timing and deterministic data delivery across network systems. This IP aids sectors ranging from aerospace to automotive by providing robust time-synchronization and schedule-aware communication networks. The core advantage of TSN lies in its detailed timing protocols, including time synchronization (IEEE 802.1AS), time-aware scheduling (IEEE 802.1Qbv), and frame replication (IEEE 802.1CB), ensuring that critical data packets are transmitted with high precision and reliability. These characteristics render TSN an essential component for applications requiring uninterrupted and synchronized data flows, especially in autonomous industrial automation and vehicular network systems. TTTech's TSN solutions extend across several domains; they are available for microcontrollers, SoCs, and network switches, offering flexible and scalable integration capabilities. The solution is reinforced by a comprehensive software stack and network scheduling tools, enhancing its applicability in designing next-generation connected systems.
MIPI Interface IP is designed to connect mobile components such as cameras and displays directly and efficiently. It supports high-speed data transfer with minimal latency, essential for modern mobile applications. These interfaces ensure compatibility with a broad range of devices by adhering to the latest MIPI standards. This makes them suitable for a variety of applications, from smartphones to advanced imaging systems. The design focuses on reducing power consumption while boosting data throughput, which is critical for mobile devices where battery life and performance are key. Engineered to accommodate evolving standards, these IP solutions ensure future-proof connectivity for evolving mobile technology applications.
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