All IPs > Memory & Logic Library > I/O Library
The I/O Library within the Memory & Logic Library category encompasses a wide range of semiconductor IPs focused on input and output interfacing. These IPs are critical for ensuring efficient data communication and integration between different parts of an electronic system. They play a pivotal role in defining how devices connect and interact with each other, which is crucial for the design of versatile and robust electronic products.
I/O Libraries are meticulously designed to support various communication protocols and standards, enabling seamless connectivity. They can include a variety of interfaces such as GPIOs (General Purpose Input/Outputs), UARTs (Universal Asynchronous Receiver-Transmitter), SPI (Serial Peripheral Interface), and I2C (Inter-Integrated Circuit) among others. Each type of interface IP ensures high compatibility and interaction efficiency, tailored to meet the specific needs of different applications ranging from simple consumer electronics to complex industrial solutions.
These semiconductor IPs are integral in reducing design time by providing pre-verified components, which developers can modularly integrate into their chip designs. By utilizing these I/O IP components, designers can significantly streamline the development process, meeting tight deadlines while achieving high-performance standards. The versatility of these IPs allows for easy customization and adaptation to various technological requirements, thus providing a flexible foundation for innovative electronic product development.
In addition to supporting various communication protocols, I/O Libraries also adhere to stringent electrical and timing specifications, ensuring reliable and consistent performance across devices. These libraries are critical in environments where precision and reliability are paramount, making them indispensable for designers focused on creating cutting-edge technology solutions. Overall, I/O Library semiconductor IPs are a cornerstone of contemporary electronics design, enabling a seamless blend of performance, compatibility, and scalability.
The xcore.ai platform by XMOS is a versatile, high-performance microcontroller designed for the integration of AI, DSP, and real-time I/O processing. Focusing on bringing intelligence to the edge, this platform facilitates the construction of entire DSP systems using software without the need for multiple discrete chips. Its architecture is optimized for low-latency operation, making it suitable for diverse applications from consumer electronics to industrial automation. This platform offers a robust set of features conducive to sophisticated computational tasks, including support for AI workloads and enhanced control logic. The xcore.ai platform streamlines development processes by providing a cohesive environment that blends DSP capabilities with AI processing, enabling developers to realize complex applications with greater efficiency. By doing so, it reduces the complexity typically associated with chip integration in advanced systems. Designed for flexibility, xcore.ai supports a wide array of applications across various markets. Its ability to handle audio, voice, and general-purpose processing makes it an essential building block for smart consumer devices, industrial control systems, and AI-powered solutions. Coupled with comprehensive software support and development tools, the xcore.ai ensures a seamless integration path for developers aiming to push the boundaries of AI-enabled technologies.
CrossBar's ReRAM Memory brings a revolutionary shift in the non-volatile memory sector, designed with a straightforward yet efficient three-layer structure. Comprising a top electrode, a switching medium, and a bottom electrode, ReRAM holds vast potential as a multiple-time programmable memory solution. Leveraging the resistive switching mechanism, the technology excels in meter-scale data storage applications, integrating seamlessly into AI-driven, IoT, and secure computing realities. The patented ReRAM technology is distinguished by its ability to perform at peak efficiency with notable read and write speeds, making it a suitable candidate for future-facing chip architectures that require swift, wide-ranging memory capabilities. Unprecedented in its energy-saving capabilities, CrossBar's ReRAM slashes energy consumption by up to 5 times compared to eFlash and offers substantial improvements over NAND and SPI Flash memories. Coupled with exceptional read latencies of around 20 nanoseconds and write times of approximately 12 microseconds, the memory technology outperforms existing solutions, enhancing system responsiveness and user experiences. Its high-density memory configurations provide terabyte-scale storage with minimal physical footprint, ensuring effective integration into cutting-edge devices and systems. Moreover, ReRAM's design permits its use within traditional CMOS manufacturing processes, enabling scalable, stackable arrays. This adaptability ensures that suppliers can integrate these memory solutions at various stages of semiconductor production, from standalone memory chips to embedded roles within complex system-on-chip designs. The inherent simplicity, combined with remarkable performance characteristics, positions ReRAM Memory as a key player in the advancement of secure, high-density computing.
Certus Semiconductor's Digital I/O solutions are engineered to meet various GPIO/ODIO standards. These versatile libraries offer support for standards such as I2C, I3C, SPI, JEDEC CMOS, and more. Designed to withstand extreme conditions, these I/Os incorporate features like ultra-low power consumption, multiple drive strengths, and high levels of ESD protection. These attributes make them suitable for applications requiring resilient performance under harsh conditions. Certus Semiconductor’s offerings also include a variety of advanced features like RGMII-compliant IO cells, offering flexibility for different project needs.
The Universal DSP Library is designed to simplify digital signal processing tasks. It ensures efficient and highly effective operations by offering a comprehensive suite of algorithms and functions tailored for various DSP applications. The library is engineered for optimal performance and can be easily integrated into FPGA-based designs, making it a versatile tool for any digital signal processing needs. The comprehensive nature of the Universal DSP Library simplifies the development of complex signal processing applications. It includes support for key processing techniques and can significantly reduce the time required to implement and test DSP functionalities. By leveraging this library, developers can achieve high efficiency and performance in their digital signal processing tasks, thereby optimizing overall system resources. Moreover, the DSP library is designed to be compatible with a wide range of FPGAs, providing a flexible and scalable solution. This makes it an ideal choice for developers seeking to create innovative solutions across various applications, ensuring that their designs can handle demanding signal processing requirements effectively.
The APB4 GPIO core from Roa Logic is a fully parameterized solution designed to provide a customizable number of general-purpose, bidirectional I/O pins. This core enables developers to define the I/O behavior precisely, adapting to a plethora of configurations to meet specific project requirements. It is essential for applications that require extensive interfacing capabilities, ensuring streamlined connectivity across multiple components. The GPIO core supports a range of operational modes, providing the flexibility to handle complex I/O operations. With capabilities like programmable drive strength and individual pin configuration, it offers a high degree of customization that can be tailored to precise application needs. Roa Logic’s offering enhances design functionality and accelerates development timelines by facilitating easy integration and application-specific optimization. This component serves as a cornerstone for designs requiring robust peripheral interaction, catering to both industrial projects and educational purposes. Its adaptability and ease of integration ensure it's an invaluable component in modern electronics design, adhering to the high standards expected in today's interconnected environments.
Spectral CustomIP encompasses an expansive suite of specialized memory architectures, tailored for diverse integrated circuit applications. Known for breadth in memory compiler designs, Spectral offers solutions like Binary and Ternary CAMs, various Multi-Ported memories, Low Voltage SRAMs, and advanced cache configurations. These bespoke designs integrate either foundry-standard or custom-designed bit cells providing robust performance across varied operational scenarios. The CustomIP products are engineered for low dynamic power usage and high density, utilizing Spectral’s Memory Development Platform. Available in source code form, these solutions offer users the flexibility to modify designs, adapt them for new technologies, or extend capabilities—facilitating seamless integration within standard CMOS processes or more advanced SOI and embedded Flash processes. Spectral's proprietary SpectralTrak technology enhances CustomIP with precise environmental monitoring, ensuring operational integrity through real-time Process, Voltage, and Temperature adjustments. With options like advanced compiler features, multi-banked architectures, and standalone or compiler instances, Spectral CustomIP suits businesses striving to distinguish their IC offerings with unique, high-performance memory solutions.
Tower Semiconductor's non-volatile memory solutions leverage cutting-edge design to enhance data retention and simplify integration within various devices. The solutions include advanced Y-Flash and e-Fuse technologies, offering reliable data storage options that retain information without a constant power supply. This makes them ideal for applications requiring persistent data, ranging from consumer electronics to critical industrial controls. The NVM solutions are designed to offer high endurance and retention periods, granting devices the capability to operate effectively across diverse environmental conditions. Y-Flash supports fast write and erase times, while e-Fuse enables secure, permanent programming options, prototyping a versatile memory solution suitable for field programming and personalization. In addition to their technological sophistication, these solutions are supported by a comprehensive suite of design resources including detailed libraries and validation data. This ensures seamless integration with existing architectures, allowing designers to rapidly bring enhancements to market. As such, Tower Semiconductor's NVM offerings signify a blend of reliability, adaptability, and innovation in modern data storage technology.
Analog Bits provides robust I/O solutions that are essential for the efficient transfer of signals between semiconductor devices and their external environment. These input/output interfaces are designed to meet the most demanding performance criteria, ensuring fast data rates and minimal signal distortion. Their I/O IP solutions can accommodate a variety of protocols, including high-speed digital interfaces and analog conversions, offering versatility and support for applications such as networking, data processing, and consumer electronics. By optimizing the signal integrity and electromagnetic compatibility, these I/Os enhance the overall system performance. Equipped with advanced features for low power consumption, these I/Os contribute to reducing the overall energy footprint of semiconductor devices, making them ideal for battery-operated devices and environmentally sensitive applications. Analog Bits' I/Os are comprehensively integrated to function seamlessly within mixed-signal environments, further broadening their application range.
CodaCache Last-Level Cache is an advanced, shared cache solution specifically designed to minimize memory latency and boost SoC performance. Its configurable nature allows it to be tailored to specific design needs, optimizing data flow and enhancing power efficiency across the chip. This cache helps overcome common SoC challenges related to timing closure, performance, and layout congestion by providing a flexible caching architecture that ensures effective data management and reliable operations. Its role in optimizing memory hierarchy enhances computational speeds and system reliability. CodaCache is particularly beneficial for applications that require rapid access to large data sets, ensuring that power consumption is minimized while maintaining high performance standards. Its versatility and efficiency make it a top choice for industries striving for high data throughput and low latency operations.
Dolphin Semiconductor's Foundation IPs are crafted to enhance the efficiency and cost-effectiveness of System-on-Chip (SoC) designs through robust offerings of embedded memories and standard-cell libraries. Specially designed for energy-efficient applications, these components help optimize space and power usage while ensuring the cutting-edge performance of modern electronic devices. Incorporated within Dolphin's Foundation IP portfolio are standard cells that allow chip designers to achieve up to 30% density gains at the cell level, compared to conventional libraries. Further, these components are engineered to support always-on applications with exceptionally low leakage rates. The Foundation IP suite optimizes SoC designs by delivering dramatically reduced leakage and area consumption, avoiding the additional cost and complexity of using a regulator. The memory compilers within Foundation IPs offer ultra-low power and high-density memory solutions, including SRAM and via-programmable ROMs. These are formulated to deliver up to 50% energy savings, providing flexibility with multi-power modes and adaptable to varied instances. With optimization for TSMC processes, Dolphin's Foundation IPs provide an essential backbone for creating innovative, efficient, and sustainable SoC products.
The Rabbit 2000 microprocessor is a compact yet powerful processor, featuring approximately 19,000 gates and a 100-pin configuration. It is a foundational component within Systemyde's suite of synthesizable IP offerings. As a versatile microprocessor, the Rabbit 2000 is designed for seamless compatibility with various technology and foundry options, ensuring adaptability in diverse design scenarios. With its comprehensive specifications and robust design, the Rabbit 2000 exemplifies Systemyde's commitment to high-quality IP development. This silicon-proven processor incorporates a range of functions that make it suitable for both FPGA and ASIC implementations. Given its optimized architecture, it performs efficient computations, making it ideal for applications requiring swift processing power. Additionally, it lays the groundwork for subsequent Rabbit microprocessors, which expand on its capabilities with enhanced features and configurations. The Rabbit 2000 benefits from Systemyde's extensive expertise in formulating high-performance, technology-independent solutions. Its adaptability is bolstered by a comprehensive suite of design packages, including a synthesizable model, test benches, and a detailed test suite for exhaustive verification. This ensures that the Rabbit 2000 is not only powerful but also reliable, supporting a wide array of embedded applications.
The SoC Platform by SEMIFIVE enables swift and minimal-effort design of system-on-chip solutions through their streamlined platforms. Built with silicon-proven IPs and optimized methodologies, these platforms significantly reduce costs and risks while ensuring a faster turnaround time. The platform supports domain-specific architectures and offers a pre-configured and verified IP pool, facilitating quick hardware and software bring-up. This platform stands out for its ability to turn ideas into silicon by leveraging SEMIFIVE’s infrastructure and IP partnerships. It promises substantial cost reduction in areas like design NRE, fabrication, and IP licenses, offering savings upwards of 50% compared to industry norms. Its rapid development process is poised to cut development times in half, maintaining high levels of design and verification reusability. The SoC Platform also minimizes engineering risks associated with the complexities of cutting-edge process technologies. By utilizing pre-verified platform IP pools and silicon-proven design components, SEMIFIVE offers a highly reliable and efficient path from concept to silicon production.
The 1D Optical Micrometers from Riftek Europe are non-contact devices specifically fashioned to measure diameters, gaps, and displacements with exceptional accuracy. They cater to the dimensional measurement needs across a wide range extending from 5 mm to 100 mm, with an impressive measuring accuracy of +/- 0.3 um aided by a sampling rate of 10000 Hz. These micrometers are indispensable in production lines where small part measurement is vital, such as mechanical engineering and electronic component manufacturing. Their high-speed data acquisition and precision allow for dynamic measurement, ensuring that product specifications are consistently met. Their efficient design and robust capabilities provide significant advantages in applications requiring quick and accurate dimensional checks, thereby minimizing manual inspection processes. The integration of this technology supports comprehensive monitoring and control frameworks that enhance overall production quality.
XMOS's xcore-200 is an advanced processor that excels in delivering multichannel audio processing and low-latency performance. Designed to support complex audio and voice processing requirements, it provides developers with the ability to integrate high-quality audio functionalities into their products. The xcore-200's architecture is engineered to allow precise control and processing capabilities, making it ideal for applications in consumer electronics and professional audio equipment. With an emphasis on reducing development time and enhancing product capabilities, the xcore-200 offers an adaptable solution equipped with an array of input and output options to meet diverse processing needs. Its powerful DSP capabilities ensure efficient processing of audio signals, enabling smoother, more reliable audio experiences for end-users. Moreover, the xcore-200 is optimized for power efficiency, supporting a range of applications without significant energy expenditure. The xcore-200 facilitates seamless integration with other technologies, making it a versatile choice for developers who need flexibility in their design process. Whether it's embedded AI functionalities or advanced audio processing demands, the xcore-200 provides a comprehensive platform for building sophisticated digital audio systems. Its capacity to manage multiple processing tasks concurrently ensures that products powered by this processor deliver robust and high-performance outcomes.
The Absolute Linear Position Sensors developed by Riftek Europe are precision instruments designed to measure and check displacements, dimensions, and surface profiles. Utilizing absolute linear encoder technology, these sensors promise an innovative approach to absolute measurement over ranges of 3 mm to 55 mm with a resolution of 0.1 um. These sensors address the demand for accurate measurement within manufacturing environments, ensuring that the run-outs and deformations are controlled to enhance product quality. They are built for reliability, delivering robust performance in challenging industrial conditions where precision is a crucial aspect of equipment and product assembly. Engineered to provide real-time feedback, these sensors aid in automating quality checks and maintaining operational efficiencies. They offer manufacturers the ability to optimize processes and reduce errors, further promoting productivity and reducing material wastage due to inaccurate measurement during production.
This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level. Also included are various open-drain I/Os and hot plug detects capable of up to 5V operation. The library also includes a wide-variety of low-capacitance RF and analog ESD. There have operating ranges from 0 to 5V protection and support a wide range of high-performance interfaces including HDMI, LVDS, USB and wireless front-ends. Also included is a range of IEC 61000-4-2 system-level ESD protection that supports digital and analog I/O cells.
Static Random-Access Memory, commonly known as SRAM, is a type of computer memory that uses latching circuitry to store each bit. Its primary feature is its ability to retain data bits in memory as long as power is being supplied. Unlike Dynamic Random-Access Memory (DRAM), which needs periodic refreshing, SRAM does not require refreshing, making it faster and more reliable for certain applications. SRAM is designed to perform read and write operations at a faster rate, often used in applications where speed is critical. It is typically employed in cache memory and other high-speed storage solutions. The architecture of SRAM includes a series of transistors arranged in a way that data is maintained in a stable state, allowing swift access and modification. This type of memory is commonly found in applications where performance and reliability are more important than capacity. SRAM's swift access time and its ability to be used at high speeds make it ideal for use in processors, networking applications, and in various embedded systems requiring rapid data access and processing capabilities.
MiniMiser articulates a revolutionary multi-port register file architecture designed with dual focuses on both low power and high performance. This product delivers over 50% reduction in power consumption, allowing developers to finely tune the power envelope through substituted standard register files with MiniMiser. Such power-saving measures help extend the design's practicality in spaces traditionally constrained by power budgets. With its stress on wide operating voltages and flexibility, MiniMiser effectively replaces standard bit cell implementations without the need for excessive clock domain adjustments, level shifters, or static timing analyses. It operates seamlessly in high-density environments where logic blocks interface and interim calculation storage is necessary, making it integral for AI-enhanced wearables. The product's architecture adapts to multiple performance modes assigning them to varying voltage levels, which keeps instantaneous power demands and total power use in check more effectively. Through these enhancements, MiniMiser innovatively cap size and energy requisites while improving the system's competitive sustainability via elongated recharge cycles and reduced thermal management overhead.
Tailored for applications requiring secure non-volatile memory, CrossBar's ReRAM as FTP/OTP Memory offers a refined solution for few-time programmable (FTP) and one-time programmable (OTP) needs. Leveraging the intrinsic properties of ReRAM technology, these applications benefit from reduced write requirements and minimized area without compromising security or performance. This ReRAM variant integrates effectively within standard CMOS processes, providing adaptability whether used independently or embedded within more complex systems. Its non-volatility and high density make it a preferred choice for secure applications where cost-efficient data integrity is essential. The technology supports diverse applications across numerous sectors including automotive, medical, and industrial systems, where quick response times and reliability are critical. The FTP/OTP ReRAM enables provisioning for physical unclonable functions (PUF), further enhancing its security capabilities. Such an implementation provides resistance to invasive attacks and maintains data integrity even under adverse conditions. These features position ReRAM as a powerful tool for managing sensitive data operations and broad pursuits in modern digital infrastructures.
X-REL is EASii IC’s line of semiconductor products explicitly tailored for extreme environments, featuring extraordinary reliability at temperatures ranging from -60°C to +230°C. These high-reliability components address the rigorous demands across sectors like oil and gas, geothermal energy, aerospace, and automotive. Available in various packages, including ceramic, metal, and, for less constrained environments, plastic, X-REL products offer extended life with minimum system cost. These components are engineered to fulfill the need for continuous operation under severe conditions, delivering five years of guaranteed reliability. X-REL’s diverse lineup encompasses power management solutions, clock and timing circuits, discrete transistors and diodes, and interfaces. The robust performance of these components, coupled with certifications like ISO9001 and EN9100, underscores their suitability for mission-critical applications, where traditional designs may falter due to adverse heat and stress.
PQSecure's Cryptographic Core serves as a comprehensive solution for implementing standardized cryptographic algorithms within system-on-chip (SoC) designs. This product is tailored for diverse applications, ranging from high-end servers to low-end embedded systems, ensuring broad compatibility. It effectively offloads both symmetric and asymmetric cryptographic operations, boosting execution efficiency. The core includes hardware accelerators capable of performing various cryptographic functions, such as true random number generation and classical public key cryptographic algorithms like ECDSA and ECDH. Incorporating next-generation post-quantum cryptographic methods, this core tackles the imminent threats posed by quantum computing. By supporting isogeny-based, lattice-based, and code-based cryptographies, it prepares systems for the quantum evolution. Furthermore, this Cryptographic Core supports secure hashing algorithms and a variety of advanced encryption standards, ensuring robust protection across different security levels recommended by standardization bodies. As an embodiment of both agility and security, it integrates seamlessly into various SoC and FPGA architectures, providing substantial power reductions compared to traditional software implementations. Designed with future-proofing in mind, PQSecure's Cryptographic Core features optional side-channel protection mechanisms validated by standard techniques, delivering DPA countermeasures without significant overhead. It boasts a comprehensive suite of verification tools, including test benches and simulation scripts, making integration into existing systems both easy and efficient. With customizable performance profiles, the Cryptographic Core is engineered to meet the demanding security requirements of tomorrow's digital environments.
Rezonent's Compute-in-Memory Technology fuses computational and memory functionalities within a single architecture to enhance processing speed and reduce power consumption. This innovative technology minimizes data movement between memory and the processor, which significantly speeds up data-intensive tasks and dramatically lowers energy usage. By utilizing sophisticated data encoding techniques, the technology optimizes storage and retrieval processes, making it ideal for AI and machine learning applications. Designed to excel in scenarios that require rapid data processing and efficient power management, Compute-in-Memory Technology addresses practical challenges faced by data centers and IoT devices. This technology effectively supports the burgeoning demand for faster processing in edge computing, where power efficiency is paramount. Its architecture is adaptable, allowing deployment across various systems, from conventional servers to cutting-edge AI models. Moreover, its integration into semiconductor designs ensures backward compatibility, offering enhanced performance without drastic changes to existing infrastructure. As data demands continue to rise, Rezonent's technology provides a scalable solution that meets the needs of modern computing applications, delivering both speed and sustainability.
The Security Protocol Accelerator from PQSecure is a pivotal component in enhancing the performance of cryptographic operations within embedded systems and processors. This accelerator facilitates the efficient execution of security protocols, such as post-quantum cryptographic algorithms, providing hardware-accelerated computation to offload intensive tasks from the main CPU. PQSecure's accelerator design focuses on optimizing the speed and efficiency of complex cryptographic tasks, including key exchange operations, digital signatures, and hashing. It is engineered to support a broad spectrum of cryptographic standards while maintaining configurability for various security and performance levels. This product stands out due to its ability to integrate seamlessly into various processor architectures and its compatibility with existing SoC and FPGA platforms. Key features of the Security Protocol Accelerator include customizable performance settings and support for both classical and post-quantum cryptographic operations. It provides significant improvements in power efficiency and computational speed, ensuring systems are prepared for future quantum challenges. With available side-channel attack countermeasures, this accelerator not only secures data but also mitigates potential vulnerabilities common in cryptographic implementations.
Riftek Europe’s 2D Optical Micrometers are designed for batch in-line dimensional measurement, offering a sophisticated solution for industries demanding precision in wire and rod measurements. The measurement scope of these micrometers spans from 8x10 mm to 60x80 mm, with outstanding accuracy up to +/-0.5 um, making them suitable for high-precision industries. These micrometers expedite measurement tasks in industrial environments, reducing manual work by automating the dimensional analysis of numerous components rapidly. By employing advanced optoelectronic technology, these devices simplify the acquisition of precise dimensional characteristics across multiple parameters. The real-time data collection capability of these devices supports seamless integration into assembly lines, enabling consistent measurement that reduces defects and assures high manufacturing standards. This contributes significantly to improving efficiency and operational throughput, aligning with the demands of fast-paced production environments.
Our Embedded ReRAM technology empowers seamless integration into existing system-on-chip (SoC) designs, delivering a compact, efficient memory solution. Designed to cater to the needs of modern electronics, it provides significant advancements in speed and power efficiency over traditional non-volatile memory (NVM) options. With the ability to operate reliably under diverse environmental conditions, this embedded solution is ideal for a wide range of applications including IoT devices, automotive systems, and smarter consumer electronics. One of the standout features of Embedded ReRAM is its eco-friendliness and scalability. Despite being embedded, it ensures a minimal footprint while maintaining high performance, making it a favorable choice for future-proof designs. This technology is engineered to enhance data retention and withstand the rigors of extreme operational environments, reinforcing its suitability for automotive and aerospace applications. The innovation behind Embedded ReRAM focuses on delivering a combination of low-power operation and high-speed performance, overcoming the limitations associated with traditional flash memory. This makes it an exceptionally versatile component in designing edge computing solutions and energy-efficient AI hardware, driving forward the evolution of next-gen intelligent devices.
The Intelligent Sensor and Power Management Platform (ISP) by IQonIC Works is engineered for sensor-driven and IoT applications that demand refined power management and efficient processing. This platform-centric solution aims to accelerate the design lifecycle, offering an integrated suite of pre-validated IP and design blocks that minimize time-to-market and development costs. ISP focuses on three core design challenges: power management, sensor interface, and software-programmable processing. It provides a comprehensive energy management framework supporting a variety of operational modes, from ultra-low power to active processing states. The platform's capability extends to harvesting and managing energy effectively, which is crucial for battery-operated or energy-scarce environments. The platform's versatility allows for scalable solutions, supporting a wide array of I/O components and processing cores such as RISC-V and ARM Cortex-M variants. It facilitates seamless expansion through industry-standard interfaces, allowing the integration of third-party components and enabling sophisticated communication and control features, ensuring adaptability and robustness in dynamically changing application environments.
MEMTECH's P-Series MRAM-DDR3 and MRAM-DDR4 solutions are crafted to offer robust non-volatile storage options optimal for environments with high performance demands, such as aerospace, industrial, and specialized SSD applications. These MRAM solutions bridge the gap between traditional memory and storage, providing the benefits of unlimited endurance and operation across broad temperature ranges. These solutions exploit the strengths of Magnetic RAM technology, ensuring data retention without power while supporting high-speed data transactions typical of DDR3 and DDR4 interfaces. This dual capability makes the P-Series MRAM particularly valuable in applications where data reliability and sustainability are paramount. The solutions are characterized by their scalable architecture capable of supporting a range of industrial and aerospace standards, ensuring reliable data storage and retrieval in challenging conditions. With their robust design, the P-Series MRAM solutions solidify MEMTECH's stance in offering cutting-edge, non-volatile memory technology for advanced computational needs.
Key ASIC provides a fundamental IP portfolio which includes essential libraries and modules necessary for integrated circuit design. The portfolio comprises standard cell libraries, general purpose I/O libraries, and compilers for SRAM, register files, and ROMs. These foundational elements support the development of versatile and robust designs, essential for high-performance applications. The Fundamental IP also includes LVCMOS I/O libraries with different voltage levels catered to varied application needs, making them adaptable for different circuit requirements. Additionally, the collection features high-voltage I/O libraries, phase-locked loop (PLL) circuits up to 500 MHz, and delay-locked loop (DLL) technology to ensure precise timing control in complex digital systems. This suite of IP supports various foundry and technology nodes, aiding designers in achieving optimal design flow for their specific needs. It addresses not only conventional design challenges but also facilitates innovations in mixed-signal solutions.
The Quazar Quad Partition Rate Memories are designed to support the next generation of high-speed, low-latency, and high-bandwidth random access memory applications. The Quazar architecture allows a single memory IC to replace multiple QDRs, providing high capacity and simplified design integration within FPGA systems. This memory solution offers flexibility through its operational modes: DEEP mode, which configures memory access as four independent SRAMs, and WIDE mode, which configures as eight independent SRAMs, enabling dynamic memory partitioning. Each Quazar IC features a high capacity of either 576Mb or 1Gb, with operational modes that improve system bandwidth and reduce board complexity by utilizing fewer serial SERDES connections. This leads to lower costs and simpler board designs. The use of dual-port memory supports advanced applications where high throughput and data integrity are paramount, such as network switches and data planes. The Quazar memory systems greatly enhance system-level performance by offering increased memory bandwidth and simplified FPGA interfacing through the MoSys-supplied RTL Memory Controller. This controller ensures efficient management of high-speed SERDES interfaces while maintaining system integrity, positioning the Quazar memory as an ideal replacement for traditional QDR memory configurations.
The IPM-BCH focuses on ensuring data reliability through its robust encoder/decoder capabilities. Rooted in the principles of Bose–Chaudhuri–Hocquenghem (BCH) coding, this IP module is engineered to facilitate error correction in a wide range of storage applications. The IPM-BCH's design allows for full customization, enabling users to specify parameters that best suit their project requirements. Incorporating the IPM-BCH in storage systems enhances their ability to handle and correct errors, which is crucial for maintaining data integrity in high-capacity environments. It serves as an essential component for developers seeking to minimize data loss and improve system reliability. The flexibility of the IPM-BCH is one of its standout features. It can be tailored to support specific channel conditions, signal characteristics, and error correction schemes. This adaptability makes it a versatile choice for applications ranging from simple storage devices to complex enterprise systems, where precision and reliability are crucial.
The Foundation IP suite by InPsytech consists of essential components crucial for building sophisticated semiconductor designs. It includes standard cells, memory compilers, and I/O interfaces that form the foundational elements of integrated circuits. Each component is meticulously designed to ensure high performance, low power consumption, and robust reliability. Standard cells within the Foundation IP are designed to optimize space and performance in IC layouts, while memory compilers offer scalable and efficient solutions for memory integration. I/O interfaces within the suite are made to ensure seamless communication across different chip components, supporting wide-ranging application needs. The Foundation IP solutions are tailored for maximal compatibility across various manufacturing processes and technologies, ensuring that semiconductor designers can achieve the highest levels of efficiency and innovation in their products. These fundamental building blocks lay the groundwork for more advanced functionality and performance in semiconductor devices.
(Information not provided)
(Information not provided)
SuperMTP® is a high-performance embedded non-volatile memory (eNVM) solution, known for its robustness and reliability. Designed for seamless integration into a variety of electronic devices, SuperMTP® can store significant data volumes without compromising on speed or efficiency. This eNVM IP is ideal for applications that require both endurance and data retention, such as in automotive and industrial devices where data integrity is crucial. The SuperMTP® technology allows for multiple program/erase cycles, ensuring that it meets the demanding needs of modern electronic systems. Its architecture is optimized for energy efficiency, making it a suitable choice for battery-operated devices. By offering high-speed data programming and retrieval, SuperMTP® enhances the overall performance and reliability of the host device. Actt’s SuperMTP® has been tailored to provide excellent performance in adverse conditions, holding up against variations in environmental and operational factors. The solution’s reliability makes it a preferred choice for designers focused on developing durable and long-lasting electronic products.
(Information not provided)
This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic. It includes support cells for all power domains: 0.8V, 1.8V, and I/O and incorporates latch-up immune, JEDEC-compliant ESD structures. The library is designed for flip-chip packaging and includes vertical and horizontal variants to support all die edge orientations. All power domains include integrated power-on control (POC) cells for safe and reliable sequencing.
This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD. The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. Cells for I/O and core power and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The library includes pads for analog signals and a 6.5V one-time-programming voltage. The GPIO can do TX and RX up to 100MHz. The ODIO is I2C compliant. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications. Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications. The I/O macro seamlessly integrates with the TSMC 1.0V I/O Library, sharing a compatible VDDA and VSSA bus structure for streamlined power management. Designed with a 14-bondpad ESD macro, including two differential pairs and dedicated power/ground cells, it provides a robust 0.8V VDDA power domain with a 0V ground reference. Engineered for reliability, the library avoids minimum-width metal traces and adheres to enhanced via/contact recommendations for long-term durability. With Cadence OA database compatibility, the library supports Spectre and auCdl views, enabling seamless simulation, LVS verification, and integration into standard design flows.
This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high and low-voltage modes. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. It has a sleep function which - when enabled - puts the I/O into an ultra-low power state and latches the I/O in the previous state. Cells for I/O, core power, and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The GPIO can do TX and RX up to 150MHz. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This library is a mixed Digital and Analog library built for the TSMC 65nm process. It is based around a Fail-Safe General Purpose Input/Output (FSGPIO) cell that is compatible with both I2C and I3C protocols. The FSGPIO operates with a power supply of 1.0 to 1.2V and can tolerate external signals up to 3.3V. The library contains all the power, ground, and ESD cells to support the FSGPIO as well as an Analog I/O cell. The cells are laid out in an inline wirebond format.
This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. All GPIO types are classified based on speed: 25MHz, 75MHz and 150MHz. All GPIO speed variants can operate at different post-driver voltage, which can be set at the system level and dynamically changed in the system if needed. The I/O includes a weak pull-up or pull-down resistor (approx. 60 Ohms). The ODIO is designed for lower speed interfaces but can be used as a high-voltage, high-speed input at up to 100MHz. The library is designed to allow for independent power sequences of any I/O cell, which is accomplished with an intrinsic power-on-control architecture. In the case of GPIO and ODIO, only when all powers are up and detected as ON, will the I/Os begin to function, otherwise they will remain in a high impedance state. Beyond standard ESD protection, the library is tolerant to 61000-4-2 IEC standard to 2kV.
This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function. The library includes an LDO to generate a 1.8V reference which has been optimized for use with the 3.3V GPIO. The library incorporates radiation-hardened ESD cells, which are silicon-proven. A fail-safe GPI allows user to interface with bus-type protocols like I2C. All cells support independent power sequencing and integrate power-on-control circuitry for a clean low-leakage power-up. A selectable Schmitt trigger receiver adds input flexibility, while a 50K ohm pull-up or pull-down resistor is available for termination configurations. The library is enriched with feed-through, filler, transition, and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This silicon-proven, I/O Library features a 5V General Purpose I/O, 5V Open-Drain I/O, 5V Analog I/O, 5V Power Supply and an area efficient 5V ESD protection scheme. The functional cells in the library (GPIO & ODIO) feature an Output Enable pin which, when de-asserted, place the I/O in a HiZ state, and can control multiple modes of output operation with the Output Mode Control pins. The input RX path for this library all have selectable operations between a Schmitt trigger input with hysteresis, a standard buffer with no hysteresis, and a low input voltage mode that can receive a voltage level much lower than the I/O supply without causing metastability or large leakage current. The library has no poly orientation limitations and can be used in any orientation. The library cells are only built up to metal three, but include an metal 4 pad anchor that can be overlaid with either a wirebond or connected to a BUMP. ESD design level are 2kV HBM, 500V CDM and +/-125mA Latch-up.
This flip-chip compatible library in Dongbu HiTek 130nm features a fail-safe GPIO, two standard GPIOs, a 5V GPI, and 5V I2C-compliant ODIO. The GFGPIO is a highly configurable 5V tolerant, multi-voltage, multi=-protocol I/O. The standard GPIO, both regular and reduced footprint, in this library is a highly configurable 5V tolerant, multi-voltage, multi-protocol I/O. The library’s GPI is a highly configurable general-purpose input cell which features three selectable input modes, three selectable resistive termination options, and a wide supply range. The library’s ODIO is a 5V I2C-compliant ODIO which features standard mode, fast-mode, and fast-mode plus, as well as selectable input modes, drive strength control and robust 2kV HBM protection. The library also supports I3C, SPI and QSPI standards. The library includes all layout and support cells. ESD targets are 2kV HBM and 500V CDM.
This library is a production-quality, silicon-proven I/O library in GlobalFoundries 65/55nm technology. The library offers a 3.3V GPIO with two selectable inputs, slew rate control, and an optional active tri-state, as well as a GPIO with an ultra-wide supply range and an optional glitch filter. The library also includes a 1.2V ODIO with two slew rate options as well as a 3.3V ODIO with a 5V tolerance. All I/Os have highly programmable POC options and active pull up/down. The library is compliant with ANSI/JEDEC/ESDA JS-001-2014 ESD standards.
A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor. Four selectable drive strengths are offered (25 235MHz @ 1.8V, 10pF) to optimize across SS) currents & power. The output driver exhibits 50 ((20%) termination across PVT to reduce reflections at higher operating frequencies. Supply cells for VDDIO, VREF, and core VDD include necessary built in ESD circuitry. A 5VI2C / SMBUS open drain (fail safe) cell, 5V OTP, programming gate cell and 1.8V & 3.3V analog cells with ESD protection are included. The library features protection break cells to allow for separate grounds while maintaining ESD robustness. ESD design targets 2kV HBM, & 50 0V CDM, yet this library has constantly demonstrated 4kV HBM. This library can also support 2kV IEC 6100-4-2 system ESD with appropriate integration.
This silicon-proven Wirebond compatible library in Dongbu HiTek 110nm features a multi-voltage, multi-standard General Purpose Input Output with an Open-Drain Input Output capability, that targets the I2C standard. The library is built as a Fail- Safe I/O design. There is no poly-orientation for this library. The library features an Analog Mux, which allows for core direct access to the bondpad, either to drive externally a signal or receive a signal from the PAD. The I/O Library is compliant with standards regarding all 1.2V, 1.8V, and 3.3V operation. The library can support various standards, including I3C, I2C, SPI and QSPI. ESD targets are 2kV HMB and 500V CDM.
This I/O Library, developed on GlobalFoundries 55nm CMOS, delivers a complete suite of digital and analog I/O solutions with robust 2 kV HBM / 500 V CDM ESD protection and latch-up immunity. The library includes 1.83.3 V GPIOs supporting GMII and LVCMOS standards, I2C-compliant ODIOs, and flexible analog I/Os (ANA/DANA) with integrated ESD. Complemented by a full set of power, filler, corner, and transition cells, the VZ55 library enables reliable padring construction across mixed-signal designs. With wide voltage support, industrial temperature range (-40C to 125C), and cross-domain ESD protection, VZ55 provides a scalable, production-ready I/O platform for advanced SoC integration.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
No credit card or payment details required.
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!