All IPs > Multimedia > MPEG / MPEG2
The MPEG and MPEG2 categories of semiconductor IPs are essential for managing digital video compression and playback in a variety of multimedia applications. These IPs are designed to facilitate efficient encoding, decoding, and transmission of video content, leveraging the capabilities of the well-established MPEG and MPEG2 standards. The technology serves as a backbone for many digital video products, enabling manufacturers to deliver high-quality video experiences in consumer electronics, broadcasting, and streaming services.
MPEG, which stands for Moving Picture Experts Group, encompasses a suite of standards for audio and video compression and transmission. MPEG semiconductor IPs support a wide range of functions, from basic video compression to more complex tasks like multiplexing video streams. MPEG2, an evolution of the original MPEG standard, further enhances video and audio quality and is particularly noted for its use in DVDs and digital television broadcasting. The IPs in this category are optimized for high-efficiency encoding processes, ensuring smoother playback and better bandwidth utilization.
These semiconductor IPs are crucial as they empower developers to create devices capable of handling intense video processing tasks with lower power requirements and greater speed. Companies in consumer electronics, such as TV manufacturers, set-top box designers, and digital video recorders, commonly utilize MPEG and MPEG2 IPs. Moreover, the broadcasting sector benefits significantly from their use in creating and managing content delving into formats suitable for various transmission channels.
In addition to consumer electronics and broadcasting, streaming services use MPEG and MPEG2 IPs to manage and deliver clear, sharp videos over the internet. By employing these semiconductor IPs, developers ensure compatibility with a broad range of devices and network conditions, providing flexible solutions that meet the dynamic needs of modern multimedia consumption. Whether the application demands real-time video processing or offline content delivery, MPEG and MPEG2 semiconductor IPs offer robust solutions that maintain the integrity and quality of visual content across multiple platforms.
The EZiD211, also known as Oxford-2, is a leading-edge demodulator and modulator developed by EASii IC to facilitate advanced satellite communications. It embodies a sophisticated DVB-S2X wideband tuner capable of supporting LEO, MEO, and GEO satellites, integrating proprietary features like Beam Hopping, VLSNR, and Super Frame applications. With EZiD211 at the helm, satellite communications undergo a transformation in efficiency and capacity, addressing both current and future demands for fixed data infrastructures, mobility, IoT, and M2M applications. Its technological forefront facilitates seamless operations in varied European space programs, validated by its full production readiness. EZiD211's design offers a unique capability to manage complex satellite links, enhance performance, and ensure robust and reliable data transmission. EASii IC provides comprehensive support through evaluation boards and samples, allowing smooth integration and testing to meet evolving satellite communication standards.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
The JPEG Encoder is a versatile and efficient solution for image compression applications. This encoder is designed to handle high-quality image formats, supporting pixel depths of up to 12 bits. It excels in delivering low-latency performance, crucial for applications requiring fast image processing such as those found in machine vision setups. Its capability to function in standard FPGA environments makes it a cost-effective option for diverse projects. The encoder comes in different configurations, each tailored for specific needs. The L1 configuration offers a monochrome multiplex pipeline, capable of operating at a pixel clock rate of 150 MHz, ideal for Spartan6 platforms. For enhanced image quality, the L2 configuration supports dual-pipe processing for high-quality output like YUV422 at frame rates up to 60fps. This configuration can be optimized for higher pixel clocks, up to 200 MHz, on custom platforms. Beyond its encoding prowess, the JPEG Encoder integrates seamlessly within network environments, supporting UDP/Ethernet streaming. This feature is complemented by comprehensive reference designs for camera systems, ensuring robust performance across various platforms. Whether you need a standalone IP or an integrated part of a broader SoC solution, this encoder offers the flexibility and reliability needed in modern digital imaging applications.
The JPEG2000 Video Compression Solution from StreamDSP offers a highly versatile compression framework capable of both lossless and lossy compression within a single codestream. Designed to support high-quality and high-compression-rate applications, this solution integrates seamlessly into a wide range of FPGA platforms. It stands out by enabling compression and decompression tasks to be performed directly within the FPGA, eliminating the need for external processors and reducing system complexity. This capability is particularly beneficial for applications such as digital cinema, surveillance, and archival digital imaging, where maintaining high fidelity while minimizing storage is critical.
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
The MPEG-H Audio System is an advanced audio codec system designed for television and virtual reality applications. It delivers immersive, high-quality sound that enhances user experiences by providing dynamic and interactive audio environments. This technology is a staple in broadcast and VR industries, known for its ability to offer personalized soundscapes and adjust sound levels and positions in real time. MPEG-H Audio works across various platforms, offering compatibility with modern broadcasting standards, making it a preferred choice for broadcasters seeking to upgrade their audio offerings. Its seamless integration into devices elevates content delivery, supporting the next-generation TV audio standards worldwide and ensuring a comprehensive auditory experience for viewers. Beyond its technical superiority, the MPEG-H Audio System is also recognized for its scalability and adaptiveness in diverse application conditions, ranging from live broadcasts to VR environments. By enabling customizable audio settings, it provides individual listeners with tailored audio experience, making it a cutting-edge tool for content creators focused on maximizing audience engagement through sound.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
The v-MP6000UDX is a versatile visual processing unit designed to power deep learning, computer vision, and video coding needs all through a single, unified architecture. This processor excels at handling high-performance tasks on embedded systems, ensuring efficiency in both power and silicon area utilization. As industries seek to integrate more sophisticated AI-driven capabilities, the v-MP6000UDX stands out by providing a comprehensive solution that runs all forms of embedded computing tasks seamlessly. A significant advantage of the v-MP6000UDX is its ability to manage complex neural networks in real-time, boasting a dynamically programmable nature that surpasses hardwired counterparts in flexibility and longevity. It facilitates the concurrent execution of various computational workflows such as signal and image processing without the traditional need for multiple hardware units, thereby reducing overall system complexity and enhancing power efficiency. The processor's architecture is particularly noteworthy for its scalability, supporting configurations from a minimal core count to over a thousand cores on a single chip. This makes the v-MP6000UDX adaptable for a wide spectrum of applications ranging from low-powered sensors to high-performance computing setups. Its support for multiple software environments and AI frameworks adds an extra layer of versatility, allowing developers to optimize and deploy a broad variety of deep learning models efficiently.
The High Performance FPGA PCIe Accelerator Card by Korusys integrates Intel's Arria 10 1150 GX FPGA, elevating computational power and efficiency. It offers a high throughput PCIe 3.0 (x8) host interface and supports bi-directional Quad 3G SDI, up to 4k UHD video handling, and GenLock over SDI. With dual DDR3 banks, this card ensures superior memory performance and is adaptable to various high-end applications. Suitable for standalone use or bundled with Korusys' IPr products, it meets the demands of advanced signal processing tasks and complex computations in a professional setting.
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
intoPIX's JPEG 2000 codec delivers premium image quality for digital video over IP networks with advanced compression capabilities. Widely recognized for its ability to handle high bit depths and resolutions, the JPEG 2000 codec is a staple in media productions that require high visual fidelity. It offers extensive feature support for different chroma subsampling schemes and bit rates, facilitating excellence in broadcast and cinema applications. As a cornerstone technology in intoPIX's offerings, the JPEG 2000 codec emphasizes minimal latency alongside high throughput levels, making it suitable for live production and post-production environments. It is equipped to handle visually lossless compression, ensuring that the subtle nuances of high-quality video are maintained for the end viewer. This codec supports various profiles, making it highly adaptable for different video settings, and provides robust error resilience ensuring seamless streaming even in network variability situations. Its powerful processing capabilities make it ideal for sectors where image integrity is paramount, such as digital cinema and HD broadcasting.
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Aimed at providing high-quality video encoding with minimal latency, the H.264 UHD Hi422 Intra Video Encoder surpasses industrial standards by supporting 4K video encoding suited for multiple high-demand applications. Its design excellence lies in handling 10-bit YUV 4:2:2 content seamlessly, ensuring sharp color contrasts and reducing gradient banding, making it ideal for medical, broadcast, and enterprise use. The encoder excels in maintaining low latency, meeting crucial performance needs in dynamic environments such as live news broadcasting and real-time video streaming. Utilizing the Xilinx Zynq-7000 architecture allows for reduced resource consumption while ensuring top-tier video quality and efficient IP streaming.
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
This MPEG-2 Software Video Encoder by Atria Logic is tailored for low power and portable device environments, focusing on MPEG-2 main profile video encoding. It's ideal for applications that include video recorders and other embedded solutions like medical imaging systems. Comprehensive compliance with the MPEG-2 standard ensures high-quality video encoding across multiple platforms, supported by ARM processors. Optimized for industrial applications, the flexibility provided by the software enables its use across various operating systems like Linux and Windows, serving a broad spectrum of use cases, including blackbox recording systems.
Designed for nuanced audio processing, the AAC-LC and HE-AAC Audio Decoder serves a pivotal role in real-time decoding of audio streams, supporting the MPEG AAC format comprehensively. This decoder is finely tuned for deployments on both FPGA and ASIC platforms, offering flexibility and elegance in handling varied audio applications. Incorporating Coreworks' sophisticated Multimedia Platform, this audio decoder is built to manage multiple audio channels efficiently, ensuring high-quality output across diverse configurations. Such meticulous engineering ensures audio integrity is preserved while optimizing system power and area performance. The AAC-LC and HE-AAC Audio Decoder is devised to handle upgradable implementations, allowing for post-deployment enhancements that adapt to changing application dynamics. This adaptability ensures that Coreworks' decoder remains a competitive and innovative option for professional audio processing needs.
The MPEG-1/2 - Layer I/II Audio Decoder is expertly designed to address the requirements of real-time audio decoding aligned with MPEG standards. This decoder seamlessly integrates with FPGA and ASIC technologies, offering it as a flexible choice for myriad professional audio applications. Harnessing the capabilities of Coreworks' Multimedia Platform, the decoder demonstrates superior performance across multiple audio streams and configurations, achieving optimal audio quality and synchronization. This core is meticulously crafted to reduce power consumption and silicon footprint while providing comprehensive support for varied use cases. Built with adaptability in mind, the MPEG-1/2 - Layer I/II Audio Decoder can be updated post-deployment, ensuring it maintains effectiveness and meets evolving technological and application standards. This versatility fortifies its suitability as a preferred decoder for sophisticated audio processing.
The AAC-LC and HE-AAC Audio Encoder is an advanced solution for the real-time encoding of audio streams, ideal for applications requiring support of the MPEG AAC audio format. This encoder core is optimized for both FPGA and ASIC platforms, ensuring flexibility and efficiency in a variety of system environments. It supports multi-stream operations, allowing for simultaneous encoding of multiple audio channels while maintaining high synchronization and fidelity. The encoding process leverages a powerful combination of hardware and software, utilizing Coreworks' proprietary Multimedia Platform which integrates cutting-edge DSP technologies. The encoder is engineered to deliver exceptional performance across various audio configurations and is capable of handling different channel combinations as required by the application. Designed for robustness, this encoder demonstrates significant advantages in terms of low power consumption and reduced silicon area usage, achieving efficient resource management. The AAC-LC and HE-AAC Audio Encoder not only supports high-fidelity audio processing but also allows for swift adjustments post-deployment, thanks to the adaptability intrinsic to Coreworks' reconfigurable architecture.
The MPEG-1/2 - Layer I/II Audio Encoder is crafted for advanced audio stream encoding, accommodating the need for MPEG audio standardization. Positioned for real-time application in diverse environments, this encoder is built to support FPGA and ASIC integrations, presenting it as a versatile choice for professional audio setups. Functioning as a comprehensive encoding solution, this IP core exhibits robust capability in managing multi-stream operations, enabling concurrent encoding with high precision across diverse audio channels. The core's design is aligned with achieving high performance, optimized to minimize energy use and conserve silicon space, thus providing an effective solution in resource-constrained environments. This audio encoder capitalizes on Coreworks' Multimedia Platform, engaging state-of-the-art SideWorks DSP technology to enhance performance and facilitate easy updates and customizations. Such flexibility ensures the encoder's relevance and functionality remain intact, even as application demands evolve.
The MPEG-1/2 + AAC Audio Decoders deliver high-performance decoding solutions for applications demanding compatibility with both MPEG and AAC formats. Crafted for real-time operation, these decoders are ideal for FPGA and ASIC integrations, supporting a wide range of audio environments. Employing the Multimedia Platform from Coreworks, this set of decoders orchestrates efficient multi-channel processing, maintaining audio clarity and synchronization while optimizing power and area usage. This efficiency is crucial in achieving robust audio playback across diverse system architectures. Strategically designed for upgradability, these decoders can undergo enhancements following deployment, ensuring their continuous alignment with evolving requirements and technological advancements. This adaptability, paired with enriching audio experience, cements their position as front-runners in versatile audio processing.
The logiJPGD-LS, a Motion JPEG (MJPEG) Lossless Decoder, adheres to Annex H of the ISO/IEC 10918-1 JPEG standard. It is optimized for still image and video decompression applications on AMD's MPSoC, SoC, and FPGA platforms, providing high-quality image output without data loss. This decoder is designed to maintain fidelity even in demanding environments, ensuring that decompressed images preserve their original quality. It supports a variety of video applications where maintaining image integrity is critical. With its focus on lossless decompression, the logiJPGD-LS serves applications that require precision and quality, making it essential for sectors like broadcasting, video archiving, and medical imaging, where data integrity is paramount.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
No credit card or payment details required.
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!