All IPs > Network on Chip
Network on Chip (NoC) semiconductor IP is a pivotal element in the design and development of highly integrated electronic systems and chips. As devices become more complex and contain multiple processing units, effective communication through reliable interconnections is crucial. NoC IPs provide a scalable and efficient way to connect various intellectual properties (IPs) within a system on chip (SoC), enabling improved data transfer, performance, and power efficiency.
In modern multicore processor architectures, the traditional bus-based communication faces challenges with scalability, latency, and energy consumption. NoC IPs address these issues by offering packet-based communication paradigms, which are structured like networks to efficiently manage data flow between cores, memory controllers, and peripheral interfaces. This technology is vital for a range of applications including data centers, mobile processors, automotive systems, and beyond. It not only helps in breaking the bandwidth bottleneck but also enhances the overall performance of the system.
A detailed exploration of the Network on Chip category reveals various types of IPs designed to cater to different specific needs, including low-latency networks, high-bandwidth connections, and power-conserving interfaces. Developers and designers can choose from pre-verified solutions by leading vendors, ensuring reliability and reducing time to market. Functionalities offered by these IP solutions might include advanced routing algorithms, traffic prioritization, security features, and error correction mechanisms.
Furthermore, semiconductor IPs in the Network on Chip category are continuously evolving to support emerging technologies such as AI, IoT, and 5G. This makes NoC IPs not only a fundamental infrastructure element but also a key enabler of future technological advancements. Companies seeking to develop state-of-the-art, fully integrated SoCs will find the NoC IP category indispensable in constructing efficient and robust systems capable of meeting current and future demands.
Akida's Neural Processor IP represents a leap in AI architecture design, tailored to provide exceptional energy efficiency and processing speed for an array of edge computing tasks. At its core, the processor mimics the synaptic activity of the human brain, efficiently executing tasks that demand high-speed computation and minimal power usage. This processor is equipped with configurable neural nodes capable of supporting innovative AI frameworks such as convolutional and fully-connected neural network processes. Each node accommodates a range of MAC operations, enhancing scalability from basic to complex deployment requirements. This scalability enables the development of lightweight AI solutions suited for consumer electronics as well as robust systems for industrial use. Onboard features like event-based processing and low-latency data communication significantly decrease the strain on host processors, enabling faster and more autonomous system responses. Akida's versatile functionality and ability to learn on the fly make it a cornerstone for next-generation technology solutions that aim to blend cognitive computing with practical, real-world applications.
The second-generation Akida platform builds upon the foundation of its predecessor with enhanced computational capabilities and increased flexibility for a broader range of AI and machine learning applications. This version supports 8-bit weights and activations in addition to the flexible 4- and 1-bit operations, making it a versatile solution for high-performance AI tasks. Akida 2 introduces support for programmable activation functions and skip connections, further enhancing the efficiency of neural network operations. These capabilities are particularly advantageous for implementing sophisticated machine learning models that require complex, interconnected processing layers. The platform also features support for Spatio-Temporal and Temporal Event-Based Neural Networks, advancing its application in real-time, on-device AI scenarios. Built as a silicon-proven, fully digital neuromorphic solution, Akida 2 is designed to integrate seamlessly with various microcontrollers and application processors. Its highly configurable architecture offers post-silicon flexibility, making it an ideal choice for developers looking to tailor AI processing to specific application needs. Whether for low-latency video processing, real-time sensor data analysis, or interactive voice recognition, Akida 2 provides a robust platform for next-generation AI developments.
SkyeChip's Coherent Network-on-Chip (NOC) is expertly designed to manage the complexities of memory-coherent systems, allowing for scalable and area-efficient interconnect solutions. It utilizes protocols like ACE and CHI to ensure seamless data coherency across components, reducing routing congestion in sophisticated many-core processing environments. The Coherent NOC integrates with SkyeChip's Home Agent and supports interchangeable coherency handlers, which helps maintain data consistency efficiently. Operating at up to 2GHz, it supports synchronous clocking topologies, facilitating high-speed communications within and between chip components. Its adaptability makes it suitable for the latest packaging technologies, enhancing high-speed data transfer and system coherency across multi-die arrangements.
Universal Chiplet Interconnect Express, or UCIe, is a forward-looking interconnect technology that enables high-speed data exchanges between various chiplets. Developed to support a modular approach in chip design, UCIe enhances flexibility and scalability, allowing manufacturers to tailor systems to specific needs by integrating multiple functions into a single package. The architecture of UCIe facilitates seamless data communication, crucial in achieving high-performance levels in integrated circuits. It is designed to support multiple configurations and implementations, ensuring compatibility across different designs and maximizing interoperability. UCIe is pivotal in advancing the chiplet strategy, which is becoming increasingly important as devices require more complex and diverse functionalities. By enabling efficient and quick interchip communication, UCIe supports innovation in the semiconductor field, paving the way for the development of highly efficient and sophisticated systems.
The Quadric Chimera General Purpose Neural Processing Unit (GPNPU) delivers unparalleled performance for AI workloads, characterized by its ability to handle diverse and complex tasks without requiring separate processors for different operations. Designed to unify AI inference and traditional computing processes, the GPNPU supports matrix, vector, and scalar tasks within a single, cohesive execution pipeline. This design not only simplifies the integration of AI capabilities into system-on-chip (SoC) architectures but also significantly boosts developer productivity by allowing them to focus on optimizing rather than partitioning code. The Chimera GPNPU is highly scalable, supporting a wide range of operations across all market segments, including automotive applications with its ASIL-ready versions. With a performance range from 1 to 864 TOPS, it excels in running the latest AI models, such as vision transformers and large language models, alongside classic network backbones. This flexibility ensures that devices powered by Chimera GPNPU can adapt to advancing AI trends, making them suitable for applications that require both immediate performance and long-term capability. A key feature of the Chimera GPNPU is its fully programmable nature, making it a future-proof solution for deploying cutting-edge AI models. Unlike traditional NPUs that rely on hardwired operations, the Chimera GPNPU uses a software-driven approach with its source RTL form, making it a versatile option for inference in mobile, automotive, and edge computing applications. This programmability allows for easy updating and adaptation to new AI model operators, maximizing the lifespan and relevance of chips that utilize this technology.
SkyeChip's Non-Coherent Network-on-Chip (NOC) offers a performance-driven solution designed to optimize bandwidth and latency across silicon components. By minimizing wire utilization, it allows for power-efficient IC layouts, making it particularly valuable for complex chip architectures requiring robust interconnectivity. The NOC supports a range of node protocols, including AXI4 and AXI-Stream, and is engineered to facilitate seamless integration with SkyeChip's Coherent NOC for more extensive system partitioning. This NOC variant is capable of operating at frequencies up to 2GHz, accommodating high-frequency clocking topologies for source-synchronous environments. Its advanced interconnect capabilities enable efficient data bridges between 2.5D and 3D die configurations, thus supporting cutting-edge packaging innovations essential in modern electronic designs.
Eliyan's NuLink Die-to-Die (D2D) PHY products are designed to provide high-performance, low-power connectivity between chips, or 'chiplets,' in a system. Using standard organic laminate packaging, these IP cores maintain power and performance levels that would traditionally require advanced packaging techniques like silicon interposers. This eliminates the need for such technology, allowing cost-effective system design and reducing thermal, test, and production challenges while maintaining performance. Eliyan’s approach enables flexibility, allowing a broad substrate area that supports more chiplets in the package, significantly boosting performance and power metrics. These D2D PHY cores accommodate various industry standards, including UCIe and BoW, providing configurations tailor-made for optimal bump map layout, thus enhancing overall system efficiency.
aiSim 5 is a state-of-the-art automotive simulation platform designed for ADAS and autonomous driving testing. Recognized as the world's first ISO26262 ASIL-D certified simulator, it offers unparalleled accuracy and determinism in simulating various driving scenarios and environmental conditions. The simulator integrates AI-based digital twin technology and an advanced rendering engine to create realistic traffic scenarios, helping engineers verify and validate driver assistance systems. Harnessing powerful physics-based simulation capabilities, aiSim 5 replicates real-world phenomena like weather effects and complex traffic dynamics with precision. By offering a comprehensive set of 3D assets and scenarios, it allows for the extensive testing of systems in both typical and edge conditions. With its flexible and open architecture, aiSim 5 can seamlessly integrate into existing testing toolchains, supporting significant variations in sensor configurations and driving algorithms. The platform encourages innovation in simulation methodologies by providing tools for scenario randomization and synthetic data generation, crucial for developing resilient ADAS applications. Additionally, its cloud-ready architecture makes it applicable across various hardware platforms, turning simulation into a versatile resource available on inexpensive or high-end computing configurations alike.
High-Speed SerDes for Chiplets is engineered to provide exceptional interconnect solutions tailored for chiplet architectures. This product offers ultra-low power consumption while maintaining high data transfer rates, essential for modern multi-die systems. By facilitating rapid communication between chiplets, it enhances overall system efficiency and performance. This SerDes solution is optimized for integration with a range of tech nodes, ensuring compatibility with various semiconductor manufacturing processes. Its design is focused on providing robust data integrity and reducing latency, which are crucial for efficient system operation in complex, integrated circuits. High-Speed SerDes addresses the growing demand for advanced interconnect solutions in chiplet architectures, making it an indispensable tool for developing next-generation semiconductor devices. Its ability to support high data throughput while keeping power use minimal makes it a standout choice in high-performance design environments.
Ncore Cache Coherent Interconnect is designed to tackle the multifaceted challenges in multicore SoC systems by introducing heterogeneous coherence and efficient cache management. This NoC IP optimizes performance by ensuring high throughput and reliable data transmission across multiple cores, making it indispensable for sophisticated computing tasks. Leveraging advanced cache coherency, Ncore maintains data integrity, crucial for maintaining system stability and efficiency in operations involving heavy computational loads. With its ISO26262 support, it caters to automotive and industrial applications requiring high reliability and safety standards. This interconnect technology pairs well with diverse processor architectures and supports an array of protocols, providing seamless integration into existing systems. It enables a coherent and connected multicore environment, enhancing the performance of high-stakes applications across various industry verticals, from automotive to advanced computing environments.
The 2D FFT core is designed to efficiently handle two-dimensional FFT processing, ideal for applications in image and video processing where data is inherently two-dimensional. This core is engineered to integrate both internal and external memory configurations, which optimize data handling for complex multimedia processing tasks, ensuring a high level of performance is maintained throughout. Utilizing sophisticated algorithms, the 2D FFT core processes data through two FFT engines. This dual approach maximizes throughput, typically limiting bottlenecks to memory bandwidth constraints rather than computational delays. This efficiency is critical for applications handling large volumes of multimedia data where real-time processing is a requisite. The capacity of the 2D FFT core to adapt to varying processing environments marks its versatility in the digital processing landscape. By ensuring robust data processing capabilities, it addresses the challenges of dynamic data movement, providing the reliability necessary for multimedia systems. Its strategic design supports the execution of intensive computational tasks while maintaining the operational flow integral to real-time applications.
ISPido on the VIP Board is tailored for Lattice Semiconductors' Video Interface Platform, providing a runtime solution optimized for delivering crisp, balanced images in real-time. This solution offers two primary configurations: automatic deployment for optimal settings instantly upon startup, and a manual, menu-driven interface allowing users to fine-tune settings such as gamma tables and convolution filters. Utilizing the CrossLink VIP Input Bridge with Sony IMX 214 sensors and an ECP5-85 FPGA, it provides HD output in HDMI YCrCb format, ensuring high-quality image resolution and real-time calibration.
Network on Chip X, or NOC-X, is an advanced solution that facilitates communication within a chip by integrating multiple processor cores and IP blocks through a high-performance data transmission network. This IP is specifically crafted to optimize on-chip data flow, ensuring that information can be swiftly and efficiently routed to where it's needed, even in the most demanding computational environments. The NOC-X is built to support a variety of configurations, making it an adaptable choice for different semiconductor designs. It enhances system throughput while maintaining low power consumption, crucial for modern electronic devices requiring both high-speed processing and energy efficiency. By leveraging the capabilities of NOC-X, system designers can achieve superior design flexibility, accelerating the development of complex systems with multiple processing demands. This IP thus plays a role in pushing the boundaries of what’s possible in semiconductor innovation, contributing to the efficiency and performance of future technology solutions.
Packetcraft's Bluetooth LE Audio Solutions offer a full suite of host, controller, and LC3 components optimized for seamless transition to Bluetooth LE Audio. The platform supports Auracast broadcast audio and True Wireless Stereo (TWS), making it adaptable to prevalent chipsets and providing flexibility to product companies. The modular design facilitates simplified integration, ensuring companies can leverage advanced audio capabilities in a variety of applications. As Bluetooth audio technology evolves, Packetcraft remains at the leading edge, offering industry-leading solutions that cater to modern audio requirements.
FlexWay Interconnect is precisely engineered for cost-effective and low-power applications, particularly suited for Internet-of-Things (IoT) edge devices and microcontrollers. It ensures efficient data management across small to medium scale SoCs. Providing support for ISO26262, it bolsters safety and reliability in critical applications. This interconnect allows for flexible topology generation, enabling configurations that minimize wire lengths and optimize timing closures. Its inherently scalable design allows for incremental upgrades and enhancements, accommodating up to 50 network interface units for customizable connections across configurations. The technology underpinning FlexWay supports key industry protocols such as AXI and APB, making it adaptable to various design requirements. The inclusion of automatic, script-driven topology generation and mesh network editing capabilities means that design complexity is significantly reduced, easing the path from concept to production.
UTTUNGA is a high-performance PCIe accelerator card, purpose-built to amplify HPC and AI tasks through its integration with the TUNGA SoC. It effectively harnesses the power of multi-core RISC-V technology combined with Posit arithmetic, offering significant enhancements in computation efficiency and memory optimization. Designed to be compatible with a broad range of server architectures, including x86, ARM, and PowerPC, UTTUNGA elevates system capabilities, particularly in precision computing applications. The UTTUNGA card operates by implementing foundational arithmetic operations in Posit configurations, supporting multiple bit-width formats for diverse processing needs. This flexibility is further complemented by a pool of programmable FPGA gates, optimized for scenarios demanding real-time adaptability and cloud computing acceleration. These gates facilitate the acceleration of complex tasks and aid in the effortless management of non-standard data types essential for advanced AI processing and cryptographic applications. By leveraging a seamless integration process, UTTUNGA eliminates the need for data copying in host memory, thus ensuring efficient utilization of resources. It also provides support for well-known scientific libraries, enabling easy adoption for legacy systems while fostering a modern computing environment. UTTUNGA stands as a testament to the profound impact of advancing arithmetic standards like Posit, paving the way for a transformation in computational practices across industries.
ISPido offers a comprehensive set of IP cores focused on high-resolution image signal processing and tuning across multiple devices and platforms, including CPU, GPU, VPU, FPGA, and ASIC technologies. Its flexibility is a standout feature, accommodating ultra-low power devices as well as systems exceeding 8K resolution. Designed for devices where power efficiency and high-quality image processing are paramount, ISPido adapts to a range of hardware architectures to deliver optimal image quality and processing capabilities. The IP has been widely adopted in various applications, making it a cornerstone for industries requiring advanced image calibration and processing capabilities.
The Hyperspectral Imaging System offers advanced solutions for capturing detailed spectral information beyond the visible range. This system provides unmatched access to spectral imaging, making it ideal for applications requiring precise detail, such as environmental monitoring and industrial inspection. Hyperspectral imaging divides the spectrum into many bands, delivering a richer data set that enhances material identification, classification, and analysis. This technology is pivotal where high precision in spectral analysis is necessary, aiding sectors such as agriculture and defense. Capable of capturing spectral data in high resolution across multiple wavelengths, the system's applications extend to medical fields, offering improved diagnostics and insights into biological samples. Integrating state-of-the-art CMOS technology, it ensures fast, accurate data acquisition with lower power consumption.
The BlueLynx Chiplet Interconnect system provides an advanced die-to-die connectivity solution designed to meet the demanding needs of diverse packaging configurations. This interconnect solution stands out for its compliance with recognized industry standards like UCIe and BoW, while offering unparalleled customization to fit specific applications and workloads. By enabling seamless connection to on-die buses and Networks-on-Chip (NoCs) through standards such as AMBA, AXI, ACE, and CHI, BlueLynx facilitates faster and cost-effective integration processes. The BlueLynx system is distinguished by its adaptive architecture that maximizes silicon utilization, ensuring high bandwidth along with low latency and power efficiency. Designed for scalability, the system supports a remarkable range of data rates from 2 to 40+ Gb/s, with an impressive bandwidth density of 15+ Tbps/mm. It also provides support for multiple serialization and deserialization ratios, ensuring flexibility for various packaging methods, from 2D to 3D applications. Compatible with numerous process nodes, including today’s most advanced nodes like 3nm and 4nm, BlueLynx offers a progressive pathway for chiplet designers aiming to streamline transitions from traditional SoCs to advanced chiplet architectures.
IC Manage offers the Envision Real-Time Analytics Platform as a cutting-edge tool for semiconductor companies looking to analyze design and verification progress. This platform provides visual insights on extensive data sets, leveraging big data technology to offer near-real-time reports that aid efficient decision-making processes. Envision's capabilities extend to tracking millions of data points across massive datasets, providing clear visibility into the design lifecycle's various stages. This comprehensive overview enables design teams to identify trends, predict performance issues, and optimize their workflows to ensure timely project completion. Its ability to analyze vast quantities of data and provide actionable insights is invaluable for companies focusing on efficient design verification. Moreover, the platform's advanced analytics improve collaboration by offering consistent, transparent, and up-to-date information to all stakeholders. It enhances the ability to respond swiftly to potential design challenges, reducing bottlenecks, increasing accuracy, and improving overall efficiency. These features make Envision a critical asset for companies aiming to remain at the forefront of technology innovation.
The Complete 5G NR Physical Layer solution by AccelerComm is meticulously optimized for 3GPP 5G NTN networks, aiming to enhance link performance with leading SWaP (Size, Weight, and Power) parameters. This solution supports a variety of applications including broadband, D2D (Direct to Device), and defense. With its openly licensable IP, available across multiple platforms such as arm processors, AI engines, and FPGA, it ensures the necessary flexibility for broad architecture compatibility. Complete reference systems facilitate early integration and testing, while additional consulting services provide expertise in early project phases.
Thermal oxide, often referred to as SiO2, is an essential film used in creating various semiconductor devices, ranging from simple to complex structures. This dielectric film is created by oxidizing silicon wafers under controlled conditions using high-purity, low-defect silicon substrates. This process produces a high-quality oxide layer that serves two main purposes: it acts as a field oxide to electrically insulate different layers, such as polysilicon or metal, from the silicon substrate, and as a gate oxide essential for device function. The thermal oxidation process occurs in furnaces set between 800°C to 1050°C. Utilizing high-purity steam and oxygen, the growth of thermal oxide is meticulously controlled, offering batch thickness uniformity of ±5% and within-wafer uniformity of ±3%. With different techniques used for growth, dry oxidation results in slower growth, higher density, and increased breakdown voltage, whereas wet oxidation allows faster growth, even at lower temperatures, facilitating the formation of thicker oxides. NanoSILICON, Inc. is equipped with state-of-the-art horizontal furnaces that manage such high-precision oxidation processes. These furnaces, due to their durable quartz construction, ensure stability and defect-free production. Additionally, the processing equipment, like the Nanometrics 210, inspects film thickness and uniformity using advanced optical reflection techniques, guaranteeing a high standard of production. With these capabilities, NanoSILICON Inc. supports a diverse range of wafer sizes and materials, ensuring superior quality oxide films that meet specific needs for your semiconductor designs.
The SoC Platform by SEMIFIVE enables swift and minimal-effort design of system-on-chip solutions through their streamlined platforms. Built with silicon-proven IPs and optimized methodologies, these platforms significantly reduce costs and risks while ensuring a faster turnaround time. The platform supports domain-specific architectures and offers a pre-configured and verified IP pool, facilitating quick hardware and software bring-up. This platform stands out for its ability to turn ideas into silicon by leveraging SEMIFIVE’s infrastructure and IP partnerships. It promises substantial cost reduction in areas like design NRE, fabrication, and IP licenses, offering savings upwards of 50% compared to industry norms. Its rapid development process is poised to cut development times in half, maintaining high levels of design and verification reusability. The SoC Platform also minimizes engineering risks associated with the complexities of cutting-edge process technologies. By utilizing pre-verified platform IP pools and silicon-proven design components, SEMIFIVE offers a highly reliable and efficient path from concept to silicon production.
The Pipelined FFT core delivers streamlined continuous data processing capabilities with an architecture designed for pipelined execution of FFT computations. This core is perfectly suited for use in environments where data is fed continuously and needs to be processed with minimal delays. Its design minimizes memory footprint while ensuring high-speed data throughput, making it invaluable for real-time signal processing applications. By structurally arranging computations into a pipeline, the core facilitates a seamless flow of operations, allowing for one-step-after-another processing of data. The efficiency of the pipelining process reduces the system's overall latency, ensuring that data is processed as quickly as it arrives. This functionality is especially beneficial in time-sensitive applications where downtime can impact system performance. The compact design of the Pipelined FFT core integrates well into systems requiring consistent data flow and reduced resource allocation. It offers effective management of continuous data streams, supporting critical applications in areas such as real-time monitoring and control systems. By ensuring rapid data turnover, this core enhances system efficiency and contributes significantly to achieving strategic processing objectives.
The NoC Bus Interconnect by OPENEDGES is a sophisticated solution for modern semiconductor designs, providing efficient on-chip communication. This network-on-chip (NoC) architecture facilitates communication between different IP blocks within a chip, significantly enhancing data flow and reducing bottlenecks compared to traditional bus systems. This interconnect solution is designed to provide high bandwidth and low latency, supporting various data transmission protocols. It's built to be highly scalable, accommodating growing demands in complex system-on-chip (SoC) designs. The flexibility in configuration allows it to support varied application needs, making it a versatile choice for high-performance computing, data centers, and AI applications. Besides its performance advantages, the NoC Bus Interconnect offers features that ensure optimal power management, which is crucial for maintaining efficiency in energy-sensitive applications. By intelligently managing data paths and utilizing advanced buffering techniques, it effectively minimizes power usage while maximizing throughput.
IC Manage's IP Central Management System is an advanced platform designed to streamline the management of semiconductor IPs. This system is engineered to consolidate all IPs—both internal and external—into a comprehensive, searchable catalog, enhancing accessibility and security across a company's design teams. It addresses the complexities of IP reuse and integration, facilitating a more structured and efficient approach to leveraging IP assets. IP Central stands out by supporting seamless information dissemination and access control, crucial for optimizing design workflows and maximizing IP utility. It empowers organizations to effectively catalog their IP portfolios, integrating them into an enterprise-wide repository that is easily accessible yet tightly secure. This feature is particularly beneficial for design teams striving to balance diverse historical designs and methodologies in their projects. Moreover, the platform is instrumental in establishing a global IP catalog, a strategic advantage for companies looking to enhance the value of their IPs. By fostering a culture of organized and secure IP sharing, IP Central aids in reducing development time, costs while increasing reliability and design accuracy. This tool is a critical component for companies aiming to capitalize on their IP investments through improved management and deployment.
The UltraLong FFT core is specifically optimized for Xilinx FPGAs, designed to handle extensive data processing tasks with efficiency. With an architecture that accommodates large-scale FFT applications, this core is engineered to maximize throughput while minimizing memory usage. Ideal for creating high-speed data processing pipelines, the UltraLong FFT core supports advanced signal processing with unparalleled speed and accuracy, providing a reliable solution for real-time applications that demand robust performance. This FFT core integrates seamlessly with external memory systems, utilizing dual FFT engines to achieve maximum data throughput, which is typically constrained only by the bandwidth of the memory. The two FFT engines operate in tandem, allowing for rapid data computation, making it perfect for high-end computation needs. Additionally, the design's flexibility allows for easy adaptation to various signal processing demands, ensuring it meets the specific requirements of different applications. The UltraLong FFT core's design is this finely tuned integration capability, which leverages external memory and custom control logic, effectively streamlining data handling challenges. This makes it highly suited for industries requiring precise control over data transformation and real-time data processing. Whether employed in digital communication or image processing, this core offers the computational prowess necessary to maintain efficiency across complex datasets.
FlexNoC Interconnect is a cutting-edge solution designed to ensure efficient on-chip communications. This physically aware NoC addresses ISO26262 support, delivering up to a five-fold reduction in turnaround time for timing closure efforts compared to manual iterations. It's engineered for high bandwidth and load-balanced data traffic management, simplifying backend timing closure. By incorporating automatic routing and congestion management, FlexNoC maintains seamless data flow while reducing development time and project risks. With this resilient interconnect technology, designers can capitalize on advanced quality-of-service and debugging features, supporting up to 1024-bit data buses and 512 pending transaction capabilities. This practical design makes FlexNoC a preferred choice in various high-demand markets such as automotive and consumer electronics. FlexNoC's adaptable architecture supports multiple protocols including AXI, AHB, and APB, and allows for NIU tiling with options that extend flexibility. Its support for safety-critical applications ensures compliance with standards, making it suitable for markets requiring stringent reliability.
The Atrevido core from Semidynamics is a 64-bit out-of-order RISC-V processor, engineered for high performance in artificial intelligence and high-performance computing (HPC) environments. Offering extensive customization, it supports 2/3/4-wide design configurations, making it well-suited for handling intricate AI workloads that require significant processing bandwidth. Atrevido is capable of executing multiple operations simultaneously thanks to its Gazzillion Misses™ technology, which can manage up to 128 memory requests concurrently, reducing processing bottlenecks. This core is optimized for applications requiring high data throughput and is compatible with AXI and CHI interfaces, facilitating integration into advanced multiprocessor systems. Additionally, Atrevido comes vector and tensor ready, enabling it to support complex AI tasks, including key-value stores and machine learning. It includes advanced features such as vector extensions and memory interface enhancements, which improve performance in systems that demand robust computational power and flexibility.
Specializing in Network-on-Chip (NoC)-based SoC integration, this IP leverages coherent and non-coherent NoC subsystems, crucial for building scalable multi-chip solutions. By integrating several NoC platforms, it offers a robust framework for developing SoCs with enhanced connectivity and performance.
The Concrete Surface Layer Degradation Detection System addresses the critical need for evaluating the integrity of concrete structures. Utilizing advanced sensor technology, this system can detect and analyze surface layer degradation with high precision. This capability is essential for maintaining the safety and longevity of concrete infrastructures such as bridges, buildings, and pavements. By providing real-time monitoring, the system ensures early detection of potential structural weaknesses. This proactive approach enables timely maintenance and repairs, preventing costly damage and enhancing public safety. It works by employing a series of embedded sensors configured to measure various parameters indicative of surface deterioration. The system’s ability to offer real-time alerts and detailed reports makes it a vital tool for civil engineers and maintenance crews. Adaptable to different environmental conditions and surface types, it represents a versatile solution for modern infrastructure management.
The Xinglian-500 represents a significant advance in interconnect fabric technology, supporting cache coherence across multi-core CPUs and SoCs. This enables high-performance data transfer and synchronization across the network-on-chip (NoC), ensuring consistent data management within complex computing environments. As an integral element in high-performance computing systems, the Xinglian-500 aids in the smooth construction and deployment of scalable multi-core solutions. It optimizes data flow and coherence, making it essential for applications that require robust interconnectivity and data integrity. Designed to meet modern demands, the Xinglian-500 plays a crucial role in infrastructure scalability, enhancing the capabilities of data-centric applications and reducing the bottlenecks associated with traditional interconnect systems. It is particularly suitable for enterprise systems and high-computing environments that require efficient and coherent data exchange.
iNoCulator is an innovative solution designed to expedite the development of flexible and configurable Network-on-Chips (NoCs). This comprehensive platform supports NoC creation from initial concepts to system architecture, culminating in RTL simulation, emulation, and implementation. Notable for its user-friendly editing tools, iNoCulator offers complete configuration flexibility and integrates fully with existing EDA environments. This makes it an ideal choice for designers needing seamless and efficient NoC development processes. Its adaptability not only enhances the speed and efficiency of SoC architectures but also significantly reduces time-to-market.
The ZIA Stereo Vision technology is crafted for applications that require depth perception and accurate distance measuring. Utilizing stereo vision algorithms, it excels in generating 3D data from dual-camera setups, which is crucial for robots, drones, and autonomous vehicles. By employing advanced disparity mapping techniques, this technology ensures high fidelity in spatial analysis, making it particularly effective in dynamic environments. Its integration optimizes tasks that need real-time 3D depth information, aiding navigation and object placement.
Mobiveil's RapidIO Verification IP (VIP) provides a robust compliance verification solution for the RapidIO protocol. It is structured on System Verilog and compatible with the Universal Verification Methodology (UVM), allowing seamless integration with other verification environments. This IP achieves comprehensive protocol validation through logical, transport, and physical layers, employing protocol monitors for accurate checks and coverage hooks. Its extensive compliance testing ensures that designs pass all protocol scenarios, facilitating verification efforts at IP, system-on-chip, or full system levels.
The RapidIO to AXI Bridge offered by Mobiveil acts as a versatile protocol converter between RapidIO and AXI systems. It supports flexible configurations tailored to host or device roles, employing multi-channel DMA and messaging controllers for bandwidth alignment between RapidIO and system requirements. This adaptability provides significant advantages for high-performance computing settings, including defense and aerospace applications.
Orthogone's Hybrid Ultra-Low Latency FPGA Framework provides a high-performance solution explicitly crafted for ultra-low latency applications within financial trading sectors. By integrating both pre-built FPGA cores and a flexible development environment, it allows rapid prototyping and deployment of trading systems. The hybrid nature of this framework combines FPGA's high-efficiency capabilities with software's adaptive nature, leading to a seamless integration into current infrastructures. This setup not only ensures low-latency performance but also scales effortlessly as data volumes grow and market conditions change, offering a comprehensive solution for evolving trading needs.
The Intelligent Sensor and Power Management Platform (ISP) by IQonIC Works is engineered for sensor-driven and IoT applications that demand refined power management and efficient processing. This platform-centric solution aims to accelerate the design lifecycle, offering an integrated suite of pre-validated IP and design blocks that minimize time-to-market and development costs. ISP focuses on three core design challenges: power management, sensor interface, and software-programmable processing. It provides a comprehensive energy management framework supporting a variety of operational modes, from ultra-low power to active processing states. The platform's capability extends to harvesting and managing energy effectively, which is crucial for battery-operated or energy-scarce environments. The platform's versatility allows for scalable solutions, supporting a wide array of I/O components and processing cores such as RISC-V and ARM Cortex-M variants. It facilitates seamless expansion through industry-standard interfaces, allowing the integration of third-party components and enabling sophisticated communication and control features, ensuring adaptability and robustness in dynamically changing application environments.
The Mixed Radix FFT core caters to applications requiring diverse FFT lengths beyond traditional radix-2 implementations. This versatility enables users to execute FFT with different radix combinations, such as radix-3, radix-5, or radix-7, enhancing its adaptability across various transformative needs. As a result, it's a robust solution for critical data processing tasks where standard FFT cores might fall short. The architecture of the Mixed Radix FFT core supports flexible data processing requirements, ensuring compatibility with a wide range of FFT paradigms. This adaptability allows it to be integrated into bespoke systems that require specific FFT configurations, thereby expanding its usefulness in diverse applications. With efficient management of computational resources, it ensures that data transformation maintains speed without sacrificing precision. Focused on complex data transformation tasks, the Mixed Radix FFT core is designed to seamlessly accommodate FFT calculations with varying radix factors. This flexibility is invaluable for applications in advanced digital communications and multimedia processing, where data dynamics necessitate rapid yet accurate computational adjustments. By incorporating these capabilities, the core serves as a pivotal component in sophisticated digital transformation ecosystems.
Akeana's Processor System IP offers a comprehensive set of system IP blocks designed to enhance the performance and efficiency of processor systems. This product line includes a variety of sophisticated components such as Compute Coherence Blocks (CCB), coherent and non-coherent interconnect fabrics, and advanced interrupt architectures, essential for building scalable and reliable multi-core systems. Notably, the Compute Coherence Block is pivotal in facilitating coherent clusters of cores through a directory-based protocol, ensuring caches are efficiently shared among processors. This, combined with the company's adherence to AMBA specifications for interconnect fabrics, allows easy integration into existing systems, providing flexible and robust solutions for handling complex data management tasks. The IP supports a wide array of functions including the IOMMU and interrupt controllers, critical for ensuring seamless device communication and control in diversified processing environments. Akeana's in-depth understanding of processing systems enables customers to configure and deploy highly customizable solutions, achieving optimal performance through tailored IP configurations suited to their specific application needs.
Designed with an emphasis on scalability and high performance, the Xinglian-700 Interconnect Fabric is an evolved solution catering to advanced multi-core CPU and SoC configurations. It supports coherence and seamless communication across computational modules, ensuring data consistency and optimal system performance. The Xinglian-700 facilitates enhanced data interchange and network coordination, which is pivotal in constructing large-scale computing environments. Its architecture supports the deployment of complex interconnect systems by maximizing computational capabilities and minimizing latency. This interconnect fabric is particularly beneficial for high-end networking and communications infrastructure, where extensive scalability and performance are mandatory. Its design offers a comprehensive solution for the immense data handling needs seen in modern data-centric applications.
The Load Unload FFT core is crafted to facilitate efficient data handling and transformation processes, essentially managing the input and output operations of FFT-based computations. It is particularly advantageous for applications where large volumes of data must be handled smoothly and without delay. Slightly more flexible compared to traditional FFT designs, this core allows for modification according to specific project requirements, making it an excellent choice for customized signal processing solutions. Designed to optimize data throughput with minimal latency, the Load Unload FFT core supports a variety of operational configurations. This allows it to accommodate different data structures and formats, enhancing its versatility across various digital processing environments. The core's architecture ensures consistent performance, even when integrated into complex systems requiring precise data transformation capabilities. The ability to orchestrate smooth data transitions from input to output is central to the Load Unload FFT core's functionality. By effectively managing these transitions, the core reduces potential bottlenecks in data processing, ensuring that systems operate at peak efficiency. For organizations involved in signal processing, this capability translates to improved productivity and enhanced data accuracy, essential for maintaining competitive advantage.
The eFPGA IP Cores v5 from Menta represent the pinnacle of programmable logic technology. These cores are seamlessly integratable within ASICs, offering unmatched flexibility by merging the dynamic capabilities of FPGAs with the robust, compact nature of ASIC designs. At the heart of these IPs lies the capability to allow real-time reprogramming, making them indispensable for industries such as aerospace, defense, and automotive. By adopting a third-party standard cell approach, they ensure universal compatibility and ease of integration across various fabrication nodes and technologies.\n\nThese cores are highly programmable after manufacture, thereby providing a significant edge in power efficiency, security, and adaptability to different standards and features over time. Menta's innovative design enables reduced bill of materials and power consumption, aligning with sustainable technological advancement goals. Notably, its adaptable nature ensures the swift integration of custom functionalities to meet specific application requirements, crucial for fast-paced technological environments.\n\nPerformance optimization is a key aspect of Menta's eFPGA solution. By facilitating the incorporation of custom logic and specific accelerators directly within the FPGA fabric, these cores enhance computational efficiency and application-specific performance, setting a standard in the flexibility and adaptability market. Their extensive utility across edge processing, IoT, and real-time data environments reinforces the strategic advantage they provide to businesses worldwide. They continue to redefine expectations, bringing cutting-edge technology to the forefront of these sectors.
The UCIe Chiplet Interconnect is an advanced solution facilitating unparalleled communication across chiplets, ensuring efficient system scalability and integration. This interconnect standard supports high data rates ranging from 24Gbps to 32Gbps, making it essential for cutting-edge multi-chip module (MCM) designs and System in Package (SiP) technologies. Designed with flexibility, it bridges various interfaces such as AXI and CHI, providing designers with versatile options for high-throughput interconnection across different silicon pieces. Its architecture supports both die-to-die and chip-to-chip communications, essential for modern heterogeneous applications that require diverse functionalities within a compact system footprint. InnoSilicon’s UCIe solution promotes seamless data exchange and minimizes bottlenecks, improving the efficiency of systems relying heavily on parallel processing and large data transfers. This technology plays a critical role in the rapid prototyping and mass production of high-performance computing systems and AI-powered devices. Supporting current and future process nodes, the UCIe Chiplet Interconnect ensures adaptability and relevance in an evolving semiconductor landscape, contributing to the growing demand for modular and customizable semiconductor infrastructure.
The 40G MAC/PCS ULL is an advanced FPGA Ethernet MAC/PCS solution tailored for environments demanding ultra-low latency performance. This IP core, integrable within nxFramework, leverages the power of FPGA technology to deliver rapid data transmission, essential for high-frequency trading setups where speed and accuracy are paramount. Designed to handle high data throughput with minimal latency, the 40G MAC/PCS ULL ensures swift connectivity across Ethernet networks, supporting financial institutions in achieving their low-latency aspirations. It is renowned for its ability to reduce packet processing time, thereby providing a competitive edge in trading operations where every microsecond counts. The IP core is compatible with various Ethernet configurations, supporting seamless adaptation in diverse network setups. Enyx's commitment to efficiency and performance is reflected in the 40G MAC/PCS ULL, making it a cornerstone solution for developers aiming to push the limits of trading infrastructure technology.
Designed for ultra-high search performance, the Stellar Packet Classification Platform plays a crucial role in FPGA environments where the sorting and management of network traffic is required. It uses intricate access control lists (ACL) and longest prefix match (LPM) methodologies to execute complex rule-based searches. This platform supports workloads of hundreds of millions of lookups per second, with key capabilities ranging from 25Gbps to over 1Tbps. This high-speed search functionality is enhanced by support for extensive rule sets and live updates, ensuring the platform remains adaptive to real-time data and network demands. The technology's ability to handle up to 480b keys further underlines its suitability for network-intensive solutions. Its applications span a wide sphere, from 5G infrastructure and BNG setups to firewall and anti-DDoS systems. For environments needing robust IPv4/v6 address lookups and efficient routing, the Stelllar Platform provides a comprehensive solution for maintaining high reliability and security within modern data-intensive contexts.
The Parallel FFT core exemplifies high-efficiency data processing by executing FFT operations simultaneously across multiple data inputs. This design significantly accelerates data transformation tasks, making it ideal for systems that require quick and reliable FFT computations. It is especially beneficial in scenarios where large data sets must be processed in parallel, such as in telecom systems or real-time analytics platforms. With an architecture optimized for concurrent operations, the Parallel FFT core effectively distributes data processing tasks among various computational paths. This reduces the time and resources needed to achieve desired computational results, allowing for higher bandwidth applications to be realized with greater ease. The core is crafted to adjust to various signal processing requirements, maintaining consistent performance across different use cases. The integration of multiple processing streams within the Parallel FFT core enables the quick transformation of data, effectively supporting applications that demand high throughput and low latency. By leveraging advanced parallel computation techniques, the core ensures that data processing tasks are handled efficiently, supporting real-time decision-making and processing in demanding environments.
The LDACS-1 & LDACS-2 physical layer is developed for integration into communication systems requiring secure and reliable data transfer. Originally modeled in MATLAB, this physical layer design can be transitioned to Verilog to suit hardware implementation demands. As it is part of the L-band Digital Aeronautical Communication System, it serves crucial roles in ensuring efficient communication for aeronautical services, providing support for future air traffic management systems. This IP fosters innovation in radio-based communication by enhancing the range and efficiency of data transmission. Its design ensures low latency and optimized throughput, which is essential for the continuous operation of complex aeronautical communication networks. Affording great flexibility, it can be adapted to various aeronautical scenarios and integrated seamlessly with existing systems to extend their capabilities. Additionally, this physical layer IP supports a dual mode, offering both LDACS-1 and LDACS-2 compatibility, further broadening its applicability. This ensures that it meets diverse communication standards, standing as a versatile solution for future-oriented aviation communication infrastructure developments.
The 5G ORAN Base Station is set to redefine the landscape of mobile networking, vastly enhancing wireless data capacity and paving the way for innovative wireless applications. This product is designed to augment connectivity in both urban and rural settings, offering robust data handling capabilities and superior performance. By incorporating open RAN technology, it facilitates interoperability and vendor-neutral platforms, promoting innovation and flexibility. This cutting-edge base station supports a plethora of applications, allowing service providers to deliver high-speed 5G connectivity tailored to specific client needs. Its advanced architecture ensures seamless integration with existing network infrastructure, streamlining the adoption of next-gen technologies. Furthermore, the base station boasts energy-efficient design principles, presenting a sustainable option for expanding mobile broadband offerings. With its modular design, the 5G ORAN Base Station is versatile and scalable, suiting a range of deployment scenarios, from dense urban centers to remote and underserved areas. The inclusion of open interface standards accelerates innovation and reduces deployment costs, offering an optimal solution for service providers aiming to maximize their 5G network investments.
The 10G MAC/PCS ULL is a high-performance Ethernet MAC/PCS solution for FPGAs, designed to meet the rigorous demands of ultra-low latency environments in the trading sector. This IP core provides seamless integration into nxFramework, harnessing FPGA capabilities to deliver optimal speed and reliability required for today's fast-paced trading operations. This IP core is meticulously engineered for applications that require stringent latency requirements, offering high-speed data transfer rates while maintaining energy efficiency. Its architecture allows for a streamlined data flow from the network to the application layer, minimizing latency and enhancing overall system performance. Enyx's 10G MAC/PCS ULL IP core supports various Ethernet interfaces, providing the flexibility needed by developers to adapt to different network environments. Its robust design not only optimizes processing efficiency but also ensures compatibility with a wide range of hardware configurations, making it a versatile choice for financial technology developers.
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