All IPs > Processor > Building Blocks
Processor building blocks are fundamental components within the realm of semiconductor IPs that play a crucial role in the development and optimization of processors. These building blocks are indispensable for crafting sophisticated, high-performance processors required in a wide range of electronic devices, from handheld gadgets to large-scale computing systems.
Processor semiconductor IP building blocks include key elements such as arithmetic logic units (ALUs), registers, and control units, which integrate to form the central processing unit (CPU). Each of these components contributes to the overall functionality of the processor. ALUs enable the processor to perform arithmetic operations and logical decisions, while registers provide the necessary storage for quick data access. Control units are responsible for interpreting instructions and coordinating other components to execute tasks efficiently. Together, these building blocks ensure that processors perform at optimal levels, handling complex computational tasks with ease.
One of the primary uses of processor building blocks is in creating devices that require advanced computational power, such as smartphones, tablets, personal computers, and servers. These semiconductor IPs help in the design of custom processors that meet specific performance, power consumption, and cost requirements. By leveraging these building blocks, designers can develop processors that are tailored to particular applications, thereby enhancing the overall performance and efficiency of devices. This customizability also facilitates innovations in emerging technologies such as artificial intelligence, the Internet of Things (IoT), and autonomous vehicles, where processors need to handle rapidly growing workloads.
The processor building blocks category in our Silicon Hub encompasses a diverse range of semiconductor IPs that cater to different processing needs. From general-purpose processors with balanced performance to specialized processors with optimized functionalities, this category provides essential components for developing next-generation electronic solutions. By utilizing these building blocks, designers and engineers can push the boundaries of processing technology, creating more capable and efficient devices that meet the evolving demands of modern consumers and industries.
The Metis AIPU PCIe AI Accelerator Card is engineered for developers demanding superior AI performance. With its quad-core Metis AIPU, this card delivers up to 214 TOPS, tackling challenging vision applications with unmatched efficiency. The PCIe card is designed with user-friendly integration in mind, featuring the Voyager SDK software stack that accelerates application deployment. Offering impressive processing speeds, the card supports up to 3,200 FPS for ResNet-50 models, providing a competitive edge for demanding AI tasks. Its design ensures it meets the needs of a wide array of AI applications, allowing for scalability and adaptability in various use cases.
The Quadric Chimera General Purpose Neural Processing Unit (GPNPU) delivers unparalleled performance for AI workloads, characterized by its ability to handle diverse and complex tasks without requiring separate processors for different operations. Designed to unify AI inference and traditional computing processes, the GPNPU supports matrix, vector, and scalar tasks within a single, cohesive execution pipeline. This design not only simplifies the integration of AI capabilities into system-on-chip (SoC) architectures but also significantly boosts developer productivity by allowing them to focus on optimizing rather than partitioning code. The Chimera GPNPU is highly scalable, supporting a wide range of operations across all market segments, including automotive applications with its ASIL-ready versions. With a performance range from 1 to 864 TOPS, it excels in running the latest AI models, such as vision transformers and large language models, alongside classic network backbones. This flexibility ensures that devices powered by Chimera GPNPU can adapt to advancing AI trends, making them suitable for applications that require both immediate performance and long-term capability. A key feature of the Chimera GPNPU is its fully programmable nature, making it a future-proof solution for deploying cutting-edge AI models. Unlike traditional NPUs that rely on hardwired operations, the Chimera GPNPU uses a software-driven approach with its source RTL form, making it a versatile option for inference in mobile, automotive, and edge computing applications. This programmability allows for easy updating and adaptation to new AI model operators, maximizing the lifespan and relevance of chips that utilize this technology.
Leveraging a high-performance RISC architecture, the eSi-3250 32-bit core efficiently integrates instruction and data caches. This makes it compatible with designs utilizing slower on-chip memories such as eFlash. The core not only supports MMU for address translation but also allows for user-defined custom instructions, greatly enhancing its flexibility for specialized and high-performance applications.
The xcore.ai platform by XMOS is a versatile, high-performance microcontroller designed for the integration of AI, DSP, and real-time I/O processing. Focusing on bringing intelligence to the edge, this platform facilitates the construction of entire DSP systems using software without the need for multiple discrete chips. Its architecture is optimized for low-latency operation, making it suitable for diverse applications from consumer electronics to industrial automation. This platform offers a robust set of features conducive to sophisticated computational tasks, including support for AI workloads and enhanced control logic. The xcore.ai platform streamlines development processes by providing a cohesive environment that blends DSP capabilities with AI processing, enabling developers to realize complex applications with greater efficiency. By doing so, it reduces the complexity typically associated with chip integration in advanced systems. Designed for flexibility, xcore.ai supports a wide array of applications across various markets. Its ability to handle audio, voice, and general-purpose processing makes it an essential building block for smart consumer devices, industrial control systems, and AI-powered solutions. Coupled with comprehensive software support and development tools, the xcore.ai ensures a seamless integration path for developers aiming to push the boundaries of AI-enabled technologies.
The Metis AIPU M.2 Accelerator Module is designed for devices that require high-performance AI inference in a compact form factor. Powered by a quad-core Metis AI Processing Unit (AIPU), this module optimizes power consumption and integration, making it ideal for AI-driven applications. With a dedicated memory of 1 GB DRAM, it enhances the capabilities of vision processing systems, providing significant boosts in performance for devices with Next Generation Form Factor (NGFF) M.2 sockets. Ideal for use in computer vision systems and more, it offers hassle-free integration and evaluation with Axelera's Voyager SDK. This accelerator module is tailored for any application seeking to harness the power of AI processing efficiently. The Metis AIPU M.2 Module streamlines the deployment of AI applications, ensuring high performance with reduced power consumption.
The aiWare NPU (Neural Processing Unit) by aiMotive is a high-performance hardware solution tailored specifically for automotive AI applications. It is engineered to accelerate inference tasks for autonomous driving systems, ensuring excellent performance across a variety of neural network workloads. aiWare delivers significant flexibility and efficiency, capable of scaling from basic Level 2 applications to complex multi-sensor Level 3+ systems. Achieving up to 98% efficiency, aiWare's design focuses on minimizing power utilization while maximizing core performance. It supports a broad spectrum of neural network architectures, including convolutional neural networks, transformers, and recurrent networks, making it suitable for diverse AI tasks in the automotive sphere. The NPU's architecture allows for minimal external memory access, thanks to its highly efficient dataflow design that capitalizes on on-chip memory caching. With a robust toolkit known as aiWare Studio, engineers can efficiently optimize neural networks without in-depth knowledge of low-level programming, streamlining development and integration efforts. The aiWare hardware is also compatible with V2X communication and advanced driver assistance systems, adapting to various operational needs with great dexterity. Its comprehensive support for automotive safety standards further cements its reputation as a reliable choice for integrating artificial intelligence into next-generation vehicles.
The N Class RISC-V CPU IP from Nuclei is tailored for applications where space efficiency and power conservation are paramount. It features a 32-bit architecture and is highly suited for microcontroller applications within the AIoT realm. The N Class processors are crafted to provide robust processing capabilities while maintaining a minimal footprint, making them ideal candidates for devices that require efficient power management and secure operations. By adhering to the open RISC-V standard, Nuclei ensures that these processors can be seamlessly integrated into various solutions, offering customizable options to fit specific system requirements.
RAIV represents Siliconarts' General Purpose-GPU (GPGPU) offering, engineered to accelerate data processing across diverse industries. This versatile GPU IP is essential in sectors engaged in high-performance computing tasks, such as autonomous driving, IoT, and sophisticated data centers. With RAIV, Siliconarts taps into the potential of the fourth industrial revolution, enabling rapid computation and seamless data management. The RAIV architecture is poised to deliver unmatched efficiency in high-demand scenarios, supporting massive parallel processing and intricate calculations. It provides an adaptable framework that caters to the needs of modern computing, ensuring balanced workloads and optimized performance. Whether used for VR/AR applications or supporting the back-end infrastructure of data-intensive operations, RAIV is designed to meet and exceed industry expectations. RAIV’s flexible design can be tailored to enhance a broad spectrum of applications, promising accelerated innovation in sectors dependent on AI and machine learning. This GPGPU IP not only underscores Siliconarts' commitment to technological advancement but also highlights its capability to craft solutions that drive forward computational boundaries.
Syntacore's SCR3 microcontroller core is a versatile option for developers looking to harness the power of a 5-stage in-order pipeline. Designed to support both 32-bit and 64-bit symmetric multiprocessing (SMP) configurations, this core is perfectly aligned with the needs of embedded applications requiring moderate power and resource efficiency coupled with enhanced processing capabilities. The architecture is fine-tuned to handle a variety of workloads, ensuring a balance between performance and power usage, making it suitable for sectors such as industrial automation, automotive sensors, and IoT devices. The inclusion of privilege modes, memory protection units (MPUs), and cache systems further enhances its capabilities, particularly in environments where system security and reliability are paramount. Developers will find the SCR3 core to be highly adaptable, fitting seamlessly into designs that need scalability and modularity. Syntacore's comprehensive toolkit, combined with detailed documentation, ensures that system integration is both quick and reliable, providing a robust foundation for varied applications.
The Codasip RISC-V BK Core Series is designed to offer flexible and high-performance core options catering to a wide range of applications, from low-power tasks to intricate computational needs. This series achieves optimal balance in power consumption and processing speed, making it suitable for applications demanding energy efficiency without compromising performance. These cores are fully RISC-V compliant, allowing for easy customizations to suit specific needs by modifying the processor's architecture or instruction set through Codasip Studio. The BK Core Series provides a streamlining process for developing precise computing solutions, ideal for IoT edge devices and sensor controllers where both small area and low power are critical. Moreover, the BK Core Series supports architectural exploration, enabling users to optimize the core design specifically tailored to their applications. This capability ensures that each core delivers the expected power, efficiency, and performance metrics required by modern technological solutions.
The eSi-1650 is a compact, low-power 16-bit CPU core integrating an instruction cache, making it an ideal choice for mature process nodes reliant on OTP or Flash program memory. By omitting large on-chip RAMs, the IP core optimizes power and area efficiency and permits the CPU to capitalize on its maximum operational frequency beyond OTP/Flash constraints.
Designed for exceptional performance in demanding environments, the SCR6 microcontroller core integrates advanced processing capabilities with power efficiency. Featuring a 12-stage, dual-issue out-of-order pipeline and a high-performance floating-point unit (FPU), it excels in managing computationally intensive tasks with finesse and speed, making it a prime candidate for next-gen microcontroller applications. With a focus on high bandwidth and efficient throughput, the SCR6 supports scalable deployments thanks to its symmetrical multiprocessing (SMP) configurations. This design enables usage in sectors where swift processing and reliability are crucial, such as real-time industrial automation, automotive systems, and IoT platforms. Syntacore’s SCR6 benefits from a well-rounded development environment, offering support that ensures high compatibility with a variety of platforms and applications. The core exemplifies Syntacore's commitment to providing innovative solutions that embody both the potential and flexibility of the RISC-V architecture.
The eSi-1600 is a 16-bit CPU core designed for cost-sensitive and power-efficient applications. It accords performance levels similar to that of 32-bit CPUs while maintaining a system cost comparable to 8-bit processors. This IP is particularly well-suited for control applications needing limited memory resources, demonstrating excellent compatibility with mature mixed-signal technologies.
The eSi-3200, a 32-bit cacheless core, is tailored for embedded control with its expansive and configurable instruction set. Its capabilities, such as 64-bit multiply-accumulate operations and fixed-point complex multiplications, cater effectively to signal processing tasks like FFTs and FIRs. Additionally, it supports SIMD and single-precision floating point operations, coupled with efficient power management features, enhancing its utility for diverse embedded applications.
The SCR1 microcontroller core from Syntacore is an open-source, compact core tailored for deeply embedded applications. It features a straightforward 4-stage in-order pipeline, making it ideally suited for smaller, power-constrained devices where performance needs to be finely balanced with energy consumption. This core is particularly valuable in applications requiring a high degree of customization and flexibility. With a unique combination of low area footprint and efficiency, the SCR1 is a pivotal tool for developers involved in creating optimized, scalable systems, particularly in the fields of sensory data processing, IoT, and control systems. Its design architecture ensures that it can efficiently handle the demands of modern consumer electronics and other compact embedded devices. The SCR1 supports a rich ecosystem of development tools provided by Syntacore, ensuring that integration into various platforms is seamless. Syntacore's commitment to open-source development allows for a wide adoption of their core among a diverse range of projects and initiatives, enhancing the potential of the RISC-V architecture in global markets.
ISPido on the VIP Board is tailored for Lattice Semiconductors' Video Interface Platform, providing a runtime solution optimized for delivering crisp, balanced images in real-time. This solution offers two primary configurations: automatic deployment for optimal settings instantly upon startup, and a manual, menu-driven interface allowing users to fine-tune settings such as gamma tables and convolution filters. Utilizing the CrossLink VIP Input Bridge with Sony IMX 214 sensors and an ECP5-85 FPGA, it provides HD output in HDMI YCrCb format, ensuring high-quality image resolution and real-time calibration.
The iCan PicoPop® is a highly compact System on Module (SOM) based on the Zynq UltraScale+ MPSoC from Xilinx, suited for high-performance embedded applications in aerospace. Known for its advanced signal processing capabilities, it is particularly effective in video processing contexts, offering efficient data handling and throughput. Its compact size and performance make it ideal for integration into sophisticated systems where space and performance are critical.
The Universal DSP Library is designed to simplify digital signal processing tasks. It ensures efficient and highly effective operations by offering a comprehensive suite of algorithms and functions tailored for various DSP applications. The library is engineered for optimal performance and can be easily integrated into FPGA-based designs, making it a versatile tool for any digital signal processing needs. The comprehensive nature of the Universal DSP Library simplifies the development of complex signal processing applications. It includes support for key processing techniques and can significantly reduce the time required to implement and test DSP functionalities. By leveraging this library, developers can achieve high efficiency and performance in their digital signal processing tasks, thereby optimizing overall system resources. Moreover, the DSP library is designed to be compatible with a wide range of FPGAs, providing a flexible and scalable solution. This makes it an ideal choice for developers seeking to create innovative solutions across various applications, ensuring that their designs can handle demanding signal processing requirements effectively.
ISPido offers a comprehensive set of IP cores focused on high-resolution image signal processing and tuning across multiple devices and platforms, including CPU, GPU, VPU, FPGA, and ASIC technologies. Its flexibility is a standout feature, accommodating ultra-low power devices as well as systems exceeding 8K resolution. Designed for devices where power efficiency and high-quality image processing are paramount, ISPido adapts to a range of hardware architectures to deliver optimal image quality and processing capabilities. The IP has been widely adopted in various applications, making it a cornerstone for industries requiring advanced image calibration and processing capabilities.
Tachyum's Prodigy Universal Processor marks a significant milestone as it combines the functionalities of Central Processing Units (CPUs), General-Purpose Graphics Processing Units (GPGPUs), and Tensor Processing Units (TPUs) into a single cohesive architecture. This groundbreaking design is tailored to meet the escalating demands of artificial intelligence, high-performance computing, and hyperscale data centers by offering unparalleled performance, energy efficiency, and high utilization rates. The Prodigy processor not only tackles common data center challenges like elevated power consumption and stagnating processor performance but also offers a robust solution to enhance server utilization and reduce the carbon footprint of massive computational installations. Notably, it thrives on a simplified programming model grounded in coherent multiprocessor architecture, thereby enabling seamless execution of an array of AI disciplines like Explainable AI, Bio AI, and deep machine learning within a single hardware platform.
The SiFive Essential family provides a comprehensive range of embedded processor cores that can be tailored to various application needs. This series incorporates silicon-proven, pre-defined CPU cores with a focus on scalability and configurability, ranging from simple 32-bit MCUs to advanced 64-bit processors capable of running embedded RTOS and full-fledged operating systems like Linux. SiFive Essential empowers users with the flexibility to customize the design for specific performance, power, and area requirements. The Essential family introduces significant advancements in processing capabilities, allowing users to design processors that meet precise application needs. It features a rich set of options for interface customizations, providing seamless integration into broader SoC designs. Moreover, the family supports an 8-stage pipeline architecture and, in some configurations, offers dual-issue superscalar capabilities for enhanced processing throughput. For applications where security and traceability are crucial, the Essential family includes WorldGuard technology, which ensures comprehensive protection across the entire SoC, safeguarding against unauthorized access. The flexible design opens up various use cases, from IoT devices and microcontrollers to real-time control applications and beyond.
The NX Class RISC-V CPU IP by Nuclei is characterized by its 64-bit architecture, making it a robust choice for storage, AR/VR, and AI applications. This processing unit is designed to accommodate high data throughput and demanding computational tasks. By leveraging advanced capabilities, such as virtual memory and enhanced processing power, the NX Class facilitates cutting-edge technological applications and is adaptable for integration into a vast array of high-performance systems.
Engineered for a dynamic performance footprint, the SCR4 microcontroller core offers a significant advantage with its 5-stage in-order pipeline and specialized floating-point unit (FPU). This characteristic makes it ideal for applications demanding precise computational accuracy and speed, such as control systems, network devices, and automotive technologies. Leveraging 32/64-bit capability, the SCR4 core supports symmetric multiprocessing (SMP) with the added benefit of privilege modes and a comprehensive memory architecture, which includes both L1 and L2 caches. These features make it particularly attractive for developers seeking a core that enables high data throughput while maintaining a focus on power efficiency and area optimization. Syntacore has positioned the SCR4 as a go-to core for projects requiring both power and precision, supported by a development environment that is both intuitive and comprehensive. Its applicability across various industrial sectors underscores its versatility and the robustness of the RISC-V architecture that underpins it.
The eSi-3264 stands out with its support for both 32/64-bit operations, including 64-bit fixed and floating-point SIMD (Single Instruction Multiple Data) DSP extensions. Engineered for applications mandating DSP functionality, it does so with minimal silicon footprint. Its comprehensive instruction set includes specialized commands for various tasks, bolstering its practicality across multiple sectors.
Designed for integration within various industry systems, ARM M-Class based ASICs from ASIC North provide flexibility and versatility. These chips, built around the ARM Cortex-M architecture, are optimized for embedded applications, offering a balance of performance and power efficiency. They are particularly suited to IoT applications due to their robust performance metrics and modular design adaptability. ASIC North ensures that each ARM M-Class ASIC is thoroughly verified, delivering optimal reliability for deployment in complex environments.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The Origin E1 is a streamlined neural processing unit designed specifically for always-on applications in personal electronics and smart devices such as smartphones and security systems. This processor focuses on delivering highly efficient AI performance, achieving around 18 TOPS per watt. With its low power requirements, the E1 is ideally suited for tasks demanding continuous data sampling, such as camera operations in smart surveillance systems where it runs on less than 20mW of power. Its packet-based architecture ensures efficient resource utilization, maintaining high performance with lower power and area consumption. The E1's adaptability is enhanced through customizable options, allowing it to meet specific PPA requirements effectively, making it the go-to choice for applications seeking to improve user privacy and experience by minimizing external memory use.
Naneng Microelectronics offers a versatile Universal High-Speed SERDES capable of operating in a broad range of speeds from 1Gbps to 12.5Gbps. This SERDES is engineered to provide seamless and agile data transmission, underpinning critical communications infrastructure in various applications. The high-speed capabilities of this serializer/deserializer underline its suitability for high-performance networking solutions. Its flexible deployment options make it an ideal candidate for integration in a variety of system architectures, promoting a balance between speed and signal integrity. The design includes robust features to counter signal degradation and maintain the integrity of transmitted data, ensuring reliable operation across extensive data networks. Support for high data rates ensures this SERDES component meets and exceeds industry standards, delivering enhanced data throughput and supporting next-generation electronic systems. With adaptability at its core, the Universal High-Speed SERDES exemplifies comprehensive technological solutions in the semiconductor industry.
The UX Class RISC-V CPU IP epitomizes Nuclei's commitment to potent processing solutions suited for data centers and network environments. Equipped with a 64-bit architecture with integrated MMU capabilities, it is tailored for embedding into Linux-operated systems that demand high operational efficiency and reliability. The UX Class supports extensive data handling and computational tasks, ensuring seamless performance even under the rigors of data-intensive environments.
The Cyclone V FPGA with Integrated PQC Processor by ResQuant is a specialized product that comes pre-equipped with a comprehensive NIST PQC cryptography suite. This FPGA is tailored for applications requiring a robust proof-of-concept for quantum-safe implementations. It ensures seamless integration into existing systems, providing a practical platform for testing and deployment in quantum-secure environments. This product is available at a competitive price and represents an ideal starting point for entities looking to explore and adopt quantum-resilient technologies. Its configuration allows for straightforward implementation in diverse hardware infrastructures while offering a reliable option for organizations aiming to stay ahead in the evolving cyber security landscape. By incorporating the latest in cryptographic standards and ensuring vendor independence, the Cyclone V FPGA with Integrated PQC Processor by ResQuant effectively bridges current hardware technologies and future-proof security needs. It supports industry-wide applications, from IoT and ICT to automotive and military sectors, underscoring ResQuant's versatility in hardware security solutions.
The SCR5 application core by Syntacore is crafted for high-efficiency, Linux-capable applications, focusing on delivering a balance between robust performance and resource optimization. Its 9-stage in-order pipeline is augmented by an integrated Memory Management Unit (MMU), alongside L1 and L2 caches, enabling enhanced cache coherency—a critical requirement for applications that demand consistent data processing and management. This core is particularly attuned to industries such as artificial intelligence, machine learning, data centers, and mobile computing. Its seamless compatibility with SMP configurations, scaling up to 4 cores, ensures that even complex workloads can be handled efficiently without sacrificing operational efficiency or computational power. SCR5's adaptability and comprehensive support features make it an outstanding choice for developers aiming to craft high-performance applications. Syntacore's supplementary tools, including development kits and SDKs, provide a strong support ecosystem for leveraging the RISC-V architecture, empowering developers to innovate without constraints.
Nuclei's U Class RISC-V CPU IP represents a versatile computing solution engineered to handle complex processing tasks. With a 32-bit architecture augmented by a Memory Management Unit (MMU), this class is optimized for Linux environments and excels in edge computing applications. Featuring extensive configuration options, the U Class processor ensures adaptability to varied computing demands, facilitating efficient task execution across diverse scenarios.
XMOS's xcore-200 is an advanced processor that excels in delivering multichannel audio processing and low-latency performance. Designed to support complex audio and voice processing requirements, it provides developers with the ability to integrate high-quality audio functionalities into their products. The xcore-200's architecture is engineered to allow precise control and processing capabilities, making it ideal for applications in consumer electronics and professional audio equipment. With an emphasis on reducing development time and enhancing product capabilities, the xcore-200 offers an adaptable solution equipped with an array of input and output options to meet diverse processing needs. Its powerful DSP capabilities ensure efficient processing of audio signals, enabling smoother, more reliable audio experiences for end-users. Moreover, the xcore-200 is optimized for power efficiency, supporting a range of applications without significant energy expenditure. The xcore-200 facilitates seamless integration with other technologies, making it a versatile choice for developers who need flexibility in their design process. Whether it's embedded AI functionalities or advanced audio processing demands, the xcore-200 provides a comprehensive platform for building sophisticated digital audio systems. Its capacity to manage multiple processing tasks concurrently ensures that products powered by this processor deliver robust and high-performance outcomes.
TimbreAI T3 addresses audio processing needs by embedding AI in sound-based applications, particularly suitable for power-constrained devices like wireless headsets. It's engineered for exceptional power efficiency, requiring less than 300 µW to operate while maintaining a performance capacity of 3.2 GOPS. This AI inference engine simplifies deployment by never necessitating changes to existing trained models, thus preserving accuracy and efficiency. The TimbreAI T3's architecture ensures that it handles noise reduction seamlessly, offering core audio neural network support. This capability is complemented by its flexible software stack, further reinforcing its strength as a low-power, high-functionality solution for state-of-the-art audio applications.
Engineered for top-tier AI applications, the Origin E8 excels in delivering high-caliber neural processing for industries spanning from automotive solutions to complex data center implementations. The E8's design supports singular core performance up to 128 TOPS, while its adaptive architecture allows easy multi-core scalability to exceed PetaOps. This architecture eradicates common performance bottlenecks associated with tiling, delivering robust throughput without unnecessary power or area compromises. With an impressive suite of features, the E8 facilitates remarkable computational capacity, ensuring that even the most intricate AI networks function smoothly. This high-performance capability, combined with its relatively low power usage, positions the E8 as a leader in AI processing technologies where high efficiency and reliability are imperative.
The Origin E2 NPU cores offer a balanced solution for AI inference by optimizing for both power and area without compromising performance. These cores are expertly crafted to save system power in devices such as smartphones and edge nodes. Their design supports a wide variety of networks, including RNNs and CNNs, catering to the dynamic demands of consumer and industrial applications. With customizable performance ranging from 1 to 20 TOPS, they are adept at handling various AI-driven tasks while reducing latency. The E2 architecture is ingeniously configured to enable parallel processing, affording high resource utilization that minimizes memory demands and system overhead. This results in a flexible NPU architecture that serves as a reliable backbone for deploying efficient AI models across different platforms.
The Origin E6 provides a formidable edge in AI processing demands for mobile and AR/VR applications, boasting performance specifications between 16 to 32 TOPS. Tailored to accommodate the latest AI models, the E6 benefits from Expedera's distinct packet-based architecture. This cutting-edge design simplifies parallel processing, which enhances efficiency while concurrently diminishing power and resource consumption. As an NPU, it supports an extensive array of video, audio, and text-based networks, thus delivering consistent performance even under complex specifications. The E6's high utilization rates minimize wastage and amplify throughput, certifying its position as an optimal choice for forward-thinking gadgets requiring potent due to its scalable and adaptable architecture.
The YVR is a sophisticated processor designed around the AVR Instruction Set Architecture, optimized with a 2-clock machine cycle. It capitalizes on the strengths of the AVR architecture, providing enhanced processing speeds while maintaining power efficiency—a key requirement for many modern electronics. Its design ensures that it can be integrated into a wide range of applications, particularly those that demand rapid data processing alongside reliable performance. The YVR supports a variety of technological environments, offering flexibility in both legacy systems and new developments requiring robust embedded processors. Systemyde provides a complete package of design and verification resources for the YVR, ensuring high performance and dependability. This processor is a versatile choice for designers seeking a balance between speed, efficiency, and reliability in their embedded applications, making it an integral part of Systemyde’s processor offerings.
ADICSYS, a subsidiary of EASii IC, provides advanced Field Programmable Gate Array (FPGA) solutions that blend the benefits of custom FPGA and embedded FPGA technologies. With over a decade's worth of expertise in FPGA development, ADICSYS offers soft eFPGA IP which is not only highly customizable and scalable but also seamlessly integrates into standard RTL design flows. This IP is designed to be technology-independent and supports a synthesis from RTL to FPGA bitstream conversion, catering to diverse application requirements. The soft eFPGA technology from ADICSYS is celebrated for its flexibility, allowing modifications to circuits even post-production and during service. This adaptability significantly reduces design times and risks associated with errors. By enabling Programmable IPs with immediate accessibility for customization, ADICSYS supports a range of architectural parameters, from LUT count to routing density, ensuring precise adaptation to area, performance, and power constraints. The Synthesizable Programmable Core (SPC) created by ADICSYS is particularly advantageous for reducing risks associated with design errors and specification changes, making it a pivotal component in many industrial applications. ADICSYS stands out for its application of industry-standard CAD tools, guaranteeing ease in integration and adaptability for varied semiconductor projects.
The Metis AIPU Quad-Core High-Performance PCIe Card stands at the pinnacle of AI acceleration, offering an incredible 856 TOPS performance. With its architecture built around four Metis AIPUs, this card is suited for handling the most demanding AI workloads. Available in configurations with up to 64GB of memory, it supports ultra-high frame rates like 12,800 FPS for ResNet-50 and up to 38,884 FPS for MobileNet V2-1.0. This high-performance card is crafted for tasks that demand uncompromised speed and efficiency. Enhanced through convenient integration with the Voyager SDK, it simplifies the implementation of AI-driven innovation across numerous sectors.
The ONNC Compiler is a robust compilation tool designed for optimizing AI models, particularly neural networks, for efficient deployment on hardware accelerators. This compiler is capable of translating high-level AI models into optimized code that makes the best use of the underlying silicon architecture, ensuring reduced power consumption and increased processing performance. One of the key features of the ONNC Compiler is its support for a wide array of neural network models and architectures, facilitating versatile applications across different AI domains. It provides developers with flexibility and control over the compilation process, allowing for optimizations that align closely with specific hardware capabilities and constraints. The ONNC Compiler is integrated into Skymizer's suite of tools to support seamless deployment of AI solutions, reducing the complexity and time associated with bringing AI models from development stages to fully functioning applications. This integration ensures high efficiency and scalability, making it an essential tool for enterprises looking to maximize their AI hardware investments.
The High-Performance FPGA & ASIC Networking Product is engineered to seamlessly integrate into distributed systems that are essential in critical domains. This product leverages advanced hardware-based switch technology, utilizing a 10Gb backbone based on finite state machines. As a result, it guarantees high-efficiency performance metrics crucial for a range of industrial applications. Originally tailored for use in the aerospace sector, this networking product addresses key parameters such as safety certification, extensive cyber resilience, and frugality in power usage and weight. The design negates the need for conventional software-based processing, thus significantly lowering overall system workload and promoting energy efficiency, which is vital for heavily regulated sectors like avionics. Moreover, by incorporating advanced encryption capabilities using AES256 GCM and supporting an extensive array of protocols including Ethernet, AFDX, TSN, and others, the product ensures secure data handling. It also provides adaptable data aggregation and conversion features, making it an ideal match for complex system architectures requiring robust and responsive network functionalities. Exported beyond aerospace, this IP finds relevance across various sectors like automotive, naval, and infrastructure management, aligning with industry-specific needs such as cybersecurity, system integration, and compatibility with legacy systems.
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
The DF6802 is an 8-bit synthesizable MPU IP Core, software-compatible with Motorola MC6802. It features an enhanced internal architecture for approximately 4 times faster execution than the original 6802 chip at the same clock frequency. Designed with two power-saving modes (WAIT and HALT), the DF6802 is ideal for automotive and battery-driven applications. It is fully customizable, allowing for a configuration that meets specific user needs, without extra costs for unused features. The IP Core comes equipped with a fully automated testbench and a comprehensive set of test cases for smooth package validation. Moreover, the DF6802 supports DCD’s Hardware Debug System, DoCD™, which offers real-time, non-intrusive debugging across the entire SoC, including the ability to halt, run, step into, or skip instructions, and read/write data to any part of the microprocessor. With support for a wide range of interfaces such as USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, and Smart Card, the DF6802 shows versatile connectivity while ensuring efficient power and performance optimization. The DF6802 is technology agnostic, ensuring compatibility with all FPGA and ASIC vendors. It comes with extensive deliverables including synthesizable RTL, testbench environment, simulation macros, synthesis scripts, and complete technical documentation along with 12 months of technical support.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
DP8051CPU is an ultra high performance 8-bit soft core microcontroller designed by DCD-SEMI to be highly efficient in terms of speed and power consumption. With a pipelined RISC architecture, it can perform operations remarkably faster than the traditional 80C51, with its performance metrics standing up to 15.55 times its predecessor when benchmarked using Dhrystone 2.1. The architecture supports both Harvard and von Neumann configurations, increasing the flexibility for memory access and inclusion. The microcontroller is equipped with an advanced Power Management Unit, allowing it to maintain its high performance capabilities while optimizing power consumption. Targeted for carrying out operations with both fast on-chip memory and slower off-chip alternatives, it can process up to 300 million instructions per second while managing substantial code and data spaces efficiently. Furthermore, it is 100% compatible with the industry-standard 8051 microcontrollers in terms of binary operation, making it highly suitable for integration in existing systems. It boasts of supporting a wide variety of interfaces like USB, Ethernet, I2C, SPI, UART, and many others, which adds to the scope of applications, especially in portable and power-conscious devices. The microcontroller supports a comprehensive hardware debugging system (DoCD™), uniquely proposed to allow non-intrusive debugging of an operational application, offering a robust development and testing phase. With real-time capability and providing insights at various operational stages, it ensures that users can have a contained yet exhaustive overview of their designs. DCD ensures a technology-agnostic design, meaning that this IP core ensures compatibility across all prominent FPGA and ASIC vendors, providing flexibility and convenience for a wide array of users. The DP8051CPU is delivered with a complete test bench and a series of validation sets, ensuring a smooth integration within any workflow.
Digital Core Design presents the D68000-CPU32+, a soft core microprocessor compatible with the 68000's CPU32+ architecture. With a 32-bit data bus and address bus, this core is optimized for high performance program execution and includes a built-in DoCD-BDM debugger interface, making it ideal for debugging complete SoC systems. Its support for 8-, 16-, and 32-bit unaligned/aligned data-bus transfers and a vast array of addressing modes offers flexibility in complex application development. Designed for universal compatibility across FPGA and ASIC vendors, the D68000-CPU32+ is delivered with a comprehensive suite of testbenches, automatic validation tests, and sculpted documentation. The architecture boasts advanced arithmetic and logic capabilities, making it suitable for a wide array of applications, from embedded systems to complex SoCs. With licensing methods streamlined for ease of access, utilizing the D68000-CPU32+ in various contexts is both simple and efficient.
The Akeana 100 Series targets the demand for compact, energy-efficient processing in deeply embedded systems. Designed around a 32-bit RISC-V architecture, these processors are ideal for applications requiring real-time processing capability and low power usage. The series supports a variety of configurations in cache and closely-coupled memory, making it adaptable to diverse system requirements. This entry-level line is particularly suited to smart speakers, drones, and wearables, providing substantial flexibility for small-scale, power-constrained devices. The architecture of the Akeana 100 Series features a streamlined in-order execution pipeline, which minimizes power consumption without compromising on performance. With support for up to 64KB of data and instruction caches and closely-coupled memory, this processor series is versatile in handling fast-paced computational tasks involved in real-time environments. In addition to its performance capabilities, this processor line offers advanced features such as a physical memory protection unit and support for scalar cryptographic extensions, which deliver robust security and control in resource-sensitive applications. Customers benefit from the adaptability of this processor series, which can be tailored with additional custom instructions to meet specific market needs.
The Akeana 1000 Series is a versatile line of 64-bit RISC-V processors, offering significant configurability for data-intensive and high-performance applications. This midrange series provides support for multi-threading and both in-order and out-of-order microarchitectures, tailored to various industry needs from smart devices to automotive systems. Its comprehensive feature set allows for efficient operation with rich operating systems, such as Linux or Android, providing reliable computing power in diverse environments. With capabilities for scalable processing via a configurable issue width, the Akeana 1000 Series is ideal for edge AI, industrial automation, and advanced automotive applications, where high throughput and precision are crucial. Its architecture allows for flexible configuration of pipeline stages and memory management units, ensuring compatibility with a wide range of computation demands. This processor line offers built-in ECC support, ensuring data integrity in complex computational environments. The series' adaptability is further reinforced by support for physical memory protection, vector extensions, and hypervising capabilities, making it a comprehensive choice for mid-tier processing needs in modern technological ecosystems.
Offering cutting-edge performance, the Akeana 5000 Series is a 64-bit RISC-V processor line designed for ultra-high performance in demanding applications such as data centers and cloud computing. This series is optimized to support complex operating systems and rich software environments, engineered to scale across multiple cores for robust multi-threading performance. The 5000 Series is the apex of Akeana’s processor offerings, combining high frequency operation with industry-leading computational capabilities. The architecture features an advanced out-of-order 12-stage pipeline, enhancing instruction processing capabilities and overall performance. This design supports secure and efficient operations through enhanced virtual address handling and physical address protection features. With its architecture optimized for high clock frequencies and scalable core clusters, it provides unmatched computational power required for both cloud infrastructure and intensive AI training workloads. This series is distinguished by its multi-threaded design, supporting up to 10-way issue architecture, which enables it to handle diverse computational load efficiently. Its flexibility is further highlighted by options for vector cryptographic extensions and its ability to work effectively with hypervisor extensions, making the Akeana 5000 Series a premier choice for high-end processing solutions.
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