All IPs > Security IP
Security IPs are an integral category within the semiconductor industry focusing on the protection of electronic data and hardware. As technological advancements continue to proliferate across critical sectors like finance, healthcare, and automotive, securing data and hardware has never been more paramount. Security IPs are designed to provide essential security features such as encryption, secure communications, and access control to safeguard sensitive information and devices from unauthorized access and cyber threats.
Within the Security IP category, you will find robust offerings that include both hardware and software-based solutions tailored to various security needs. Content Protection Software enables secure data transmission and protects digital content from piracy and unauthorized distribution. Cryptography Cores and Cryptography Software Libraries offer foundational tools for implementing strong encryption algorithms that are crucial for securing communications and data storage.
Embedded Security Modules are integrated within semiconductor devices to facilitate secure data processing and enhance trust in device operations by preventing code tampering and unauthorized hardware modification. Platform Security solutions encompass a broad range of protective measures designed to secure the entire hardware and software ecosystem, ensuring that devices are safe from potential vulnerabilities at every level.
Additionally, Security Protocol Accelerators and Security Subsystems act as dedicated processing units to efficiently handle complex security algorithms and protocols, enhancing the performance of security operations while reducing the burden on primary CPUs. With an unpredictable security landscape, leveraging a range of specialized Security IPs allows designers and engineers to build robust, secure, and reliable semiconductor solutions that can withstand evolving cyber threats.
Akida's Neural Processor IP represents a leap in AI architecture design, tailored to provide exceptional energy efficiency and processing speed for an array of edge computing tasks. At its core, the processor mimics the synaptic activity of the human brain, efficiently executing tasks that demand high-speed computation and minimal power usage. This processor is equipped with configurable neural nodes capable of supporting innovative AI frameworks such as convolutional and fully-connected neural network processes. Each node accommodates a range of MAC operations, enhancing scalability from basic to complex deployment requirements. This scalability enables the development of lightweight AI solutions suited for consumer electronics as well as robust systems for industrial use. Onboard features like event-based processing and low-latency data communication significantly decrease the strain on host processors, enabling faster and more autonomous system responses. Akida's versatile functionality and ability to learn on the fly make it a cornerstone for next-generation technology solutions that aim to blend cognitive computing with practical, real-world applications.
The second-generation Akida platform builds upon the foundation of its predecessor with enhanced computational capabilities and increased flexibility for a broader range of AI and machine learning applications. This version supports 8-bit weights and activations in addition to the flexible 4- and 1-bit operations, making it a versatile solution for high-performance AI tasks. Akida 2 introduces support for programmable activation functions and skip connections, further enhancing the efficiency of neural network operations. These capabilities are particularly advantageous for implementing sophisticated machine learning models that require complex, interconnected processing layers. The platform also features support for Spatio-Temporal and Temporal Event-Based Neural Networks, advancing its application in real-time, on-device AI scenarios. Built as a silicon-proven, fully digital neuromorphic solution, Akida 2 is designed to integrate seamlessly with various microcontrollers and application processors. Its highly configurable architecture offers post-silicon flexibility, making it an ideal choice for developers looking to tailor AI processing to specific application needs. Whether for low-latency video processing, real-time sensor data analysis, or interactive voice recognition, Akida 2 provides a robust platform for next-generation AI developments.
The Akida IP is a groundbreaking neural processor designed to emulate the cognitive functions of the human brain within a compact and energy-efficient architecture. This processor is specifically built for edge computing applications, providing real-time AI processing for vision, audio, and sensor fusion tasks. The scalable neural fabric, ranging from 1 to 128 nodes, features on-chip learning capabilities, allowing devices to adapt and learn from new data with minimal external inputs, enhancing privacy and security by keeping data processing localized. Akida's unique design supports 4-, 2-, and 1-bit weight and activation operations, maximizing computational efficiency while minimizing power consumption. This flexibility in configuration, combined with a fully digital neuromorphic implementation, ensures a cost-effective and predictable design process. Akida is also equipped with event-based acceleration, drastically reducing the demands on the host CPU by facilitating efficient data handling and processing directly within the sensor network. Additionally, Akida's on-chip learning supports incremental learning techniques like one-shot and few-shot learning, making it ideal for applications that require quick adaptation to new data. These features collectively support a broad spectrum of intelligent computing tasks, including object detection and signal processing, all performed at the edge, thus eliminating the need for constant cloud connectivity.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features:  True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications.  Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data.  Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection.  Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification.  RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
The aiWare NPU (Neural Processing Unit) by aiMotive is a high-performance hardware solution tailored specifically for automotive AI applications. It is engineered to accelerate inference tasks for autonomous driving systems, ensuring excellent performance across a variety of neural network workloads. aiWare delivers significant flexibility and efficiency, capable of scaling from basic Level 2 applications to complex multi-sensor Level 3+ systems. Achieving up to 98% efficiency, aiWare's design focuses on minimizing power utilization while maximizing core performance. It supports a broad spectrum of neural network architectures, including convolutional neural networks, transformers, and recurrent networks, making it suitable for diverse AI tasks in the automotive sphere. The NPU's architecture allows for minimal external memory access, thanks to its highly efficient dataflow design that capitalizes on on-chip memory caching. With a robust toolkit known as aiWare Studio, engineers can efficiently optimize neural networks without in-depth knowledge of low-level programming, streamlining development and integration efforts. The aiWare hardware is also compatible with V2X communication and advanced driver assistance systems, adapting to various operational needs with great dexterity. Its comprehensive support for automotive safety standards further cements its reputation as a reliable choice for integrating artificial intelligence into next-generation vehicles.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features:  Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements.  BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment.  Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to:  Secured and Certified iSIM & iUICC  EMVco Payment  Hardware Cryptocurrency Wallets  FIDO2 Web Authentication  V2X HSM Protocols  Smart Car Access  Secured Boot  Secure OTA Firmware Updates  Secure Debug  Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
The RV12 RISC-V Processor is a highly configurable, single-core CPU that adheres to RV32I and RV64I standards. It’s engineered for the embedded market, offering a robust structure based on the RISC-V instruction set. The processor's architecture allows simultaneous instruction and data memory accesses, lending itself to a broad range of applications and maintaining high operational efficiency. This flexibility makes it an ideal choice for diverse execution requirements, supporting efficient data processing through an optimized CPU framework. Known for its adaptability, the RV12 processor can support multiple configurations to suit various application demands. It is capable of providing the necessary processing power for embedded systems, boasting a reputation for stability and reliability. This processor becomes integral for designs that require a maintainability of performance without compromising on the configurability aspect, meeting the rigorous needs of modern embedded computing. The processor's support of the open RISC-V architecture ensures its capability to integrate into existing systems seamlessly. It lends itself well to both industrial and academic applications, offering a resource-efficient platform that developers and researchers can easily access and utilize.
The AHB-Lite APB4 Bridge serves as a crucial interconnect that facilitates communication between the AMBA 3 AHB-Lite and AMBA APB bus protocols. As a parameterized soft IP, it offers flexibility and adaptability in managing system interconnections, bridging the gap between high-speed and low-speed peripherals with efficiency. The bridge's architecture is designed to maintain data integrity while transferring information across different protocol tiers. This bridge supports the implementation of a seamless transition for data exchanges, ensuring data packets are transmitted with minimal latency. It is ideal for systems that require stable connectivity across multiple peripheral interfaces, delivering a cohesive platform for system designers to enhance operational uniformity. By enabling efficient bus conversion, it supports broader system architectures, contributing to the overall efficiency of embedded designs. With its open-architecture design, the AHB-Lite APB4 Bridge caters to a wide range of applications, providing necessary adaptability to meet the unique demands of each project. Its robust design ensures that it can accommodate the complex architectures of modern embedded systems, enhancing both performance and reliability.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features:  Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security.  Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes.  SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance.  RTL Delivery: Delivered as RTL for ease of integration into SoC designs.  Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to:  Wearables  Smart/Connected Devices  Metrology  Entertainment Applications  Networking Equipment  Consumer Appliances  Automotive  Industrial Control Systems  Security Systems  Any SoC application that requires executing authenticated firmware in a simple but secure manner.
CrossBar's ReRAM Memory brings a revolutionary shift in the non-volatile memory sector, designed with a straightforward yet efficient three-layer structure. Comprising a top electrode, a switching medium, and a bottom electrode, ReRAM holds vast potential as a multiple-time programmable memory solution. Leveraging the resistive switching mechanism, the technology excels in meter-scale data storage applications, integrating seamlessly into AI-driven, IoT, and secure computing realities. The patented ReRAM technology is distinguished by its ability to perform at peak efficiency with notable read and write speeds, making it a suitable candidate for future-facing chip architectures that require swift, wide-ranging memory capabilities. Unprecedented in its energy-saving capabilities, CrossBar's ReRAM slashes energy consumption by up to 5 times compared to eFlash and offers substantial improvements over NAND and SPI Flash memories. Coupled with exceptional read latencies of around 20 nanoseconds and write times of approximately 12 microseconds, the memory technology outperforms existing solutions, enhancing system responsiveness and user experiences. Its high-density memory configurations provide terabyte-scale storage with minimal physical footprint, ensuring effective integration into cutting-edge devices and systems. Moreover, ReRAM's design permits its use within traditional CMOS manufacturing processes, enabling scalable, stackable arrays. This adaptability ensures that suppliers can integrate these memory solutions at various stages of semiconductor production, from standalone memory chips to embedded roles within complex system-on-chip designs. The inherent simplicity, combined with remarkable performance characteristics, positions ReRAM Memory as a key player in the advancement of secure, high-density computing.
The AHB-Lite Multilayer Switch by Roa Logic is a sophisticated interconnect fabric that provides high performance with low latency capabilities. Designed for extensive connectivity, it supports an unlimited number of bus masters and slaves, making it ideal for large-scale system architectures. This switch ensures data is efficiently propagated through various paths, optimizing resource allocation and throughput in complex systems. With a focus on performance, the multilayer switch is crafted to manage data traffic within high-demand environments seamlessly. Its support for multiple layers allows it to efficiently handle concurrent data transactions, facilitating effective communication between different system components. The adaptive structure and controlled latency pathways enable it to fit a multitude of applications, including those requiring rapid data transfer and processing. The AHB-Lite Multilayer Switch is engineered to integrate seamlessly into modern system architectures, enhancing throughput without compromising on signal integrity. Its robust design and flexible configuration options make it indispensable within systems necessitating dynamic connectivity solutions.
The AHB-Lite Timer module designed by Roa Logic is compliant with the RISC-V Privileged 1.9.1 specification, offering a versatile timing solution for embedded applications. As an integral peripheral, it provides precise timing functionalities, enabling applications to perform scheduled operations accurately. Its parameterized design allows developers to adjust the timer's features to match the needs of their system effectively. This timer module supports a broad scope of timing tasks, ranging from simple delay setups to complex timing sequences, making it ideal for various embedded system requirements. The flexibility in its design ensures straightforward implementation, reducing complexity and enhancing the overall performance of the target application. With RISC-V compliance at its core, the AHB-Lite Timer ensures synchronization and precision in signal delivery, crucial for systems tasked with critical timing operations. Its adaptable architecture and dependable functionality make it an exemplary choice for projects where timing accuracy is required.
The H.264 FPGA Encoder and CODEC micro footprint cores are a compact and fast solution for video compression, specifically tailored for FPGAs. This licensable IP cores support 1080p60 H.264 Baseline encoding with a single core, offering various configurations such as an H.264 Encoder, CODEC, and I-Frame Only Encoder. These cores are renowned for their small size and rapid processing capabilities, designed to be ITAR compliant for secure applications. Developers can customize these cores to achieve desired pixel depths and resolutions, ensuring adaptability to diverse project needs. With an exceptionally low 1ms latency at 1080p30, these cores are acclaimed as industry-leading in terms of both size and performance. They enhance efficiency by providing fast video processing solutions without compromising quality. The cores are particularly useful in applications demanding high-speed and high-resolution video compression in FPGA implementations. These H.264 cores come with the option for a low-cost evaluation license, providing a seamless entry into advanced video processing tasks. With customizable features, they represent a versatile choice for engineers working on applications involving intensive video encoding and decoding needs.
CrossBar's ReRAM IP Cores present a sophisticated solution for enhancing embedded NVM within Microcontroller Units (MCUs) and System-on-Chip (SoC) architectures. Designed to work with advanced semiconductors and ASIC (Application-Specific Integrated Circuit) designs, these cores offer efficient integration, performance enhancement, and reduced energy consumption. The technology seeks to equip contemporary and next-generation chip designs with high-speed, non-volatile memory, enabling faster computation and data handling. Targeting the unique needs of IoT, mobile computing, and consumer electronics, the ReRAM IP Cores deliver scalable memory solutions that exceed traditional flash memory limits. These cores are built to be stackable and compatible with existing process nodes, highlighting their versatility. Furthermore, the integration of ReRAM technology ensures improved energy efficiency, with the added benefit of low latency data access—a critical factor for real-time applications and processing. These IP cores provide a seamless route to incorporating high-performance ReRAM into chips without major redesigns or adjustments. As the demand for seamless, secure data processing grows, this technology enables manufacturers and designers to aptly meet the challenges presented by ever-evolving digital landscapes. By minimizing energy usage while maximizing performance capabilities, these IP cores hold potential for transformative applications in high-speed, secure data processing environments.
Polar ID from Metalenz offers a cutting-edge face unlock solution, using advanced meta-optic technology to provide secure, high-resolution facial recognition capabilities. It captures the unique "polarization signature" of a human face, making it resistant to both 2D photos and sophisticated 3D masks. Polar ID operates efficiently in a variety of lighting conditions, from bright daylight to dark environments, ensuring its utility extends across all smartphone models without sacrificing security or user experience. This technology replaces complex structured light modules, incorporating a single near-infrared polarization camera and active illumination source. It significantly reduces costs and footprint, supporting a broad adoption across hundreds of millions of mobile devices. With its low price point and high performance, Polar ID elevates smartphone security, offering robust protection for digital transactions and identity verification. By enabling this on an embedded platform with compatibility for Qualcomm's Snapdragon processors, Metalenz ensures widespread applicability. The key advantage of Polar ID is its affordability and ease of integration, as it eliminates the need for larger, more intrusive notches in phone designs. Its sophisticated polarization sensing means secure authentication is possible even if the user wears sunglasses or masks. Polar ID sets a new benchmark in smartphone security by delivering convenience and enhanced protection, marking it as the first polarization sensor available for smartphones.
Secure OTP by PUFsecurity offers a tamperproof data storage solution designed for the next generation of secure memory needs. It is an enhanced anti-fuse OTP memory that provides secure storage for key data across various forms, ensuring that data in transit, use, or rest remains protected. This technology integrates physical macros, a digital RTL controller, and a resilient anti-tamper shell to guard against hardware attacks. As IoT devices become increasingly susceptible to early-stage attacks, Secure OTP presents a reliable means to safely store sensitive data such as keys and boot code. By transitioning to this tamperproof storage format, devices can effectively mitigate vulnerabilities inherent in legacy storage systems, fortifying data security at the hardware level.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
Securyzr iSSP is an integrated Security Services Platform designed by Secure-IC to offer comprehensive lifecycle management of device security. It provides zero-touch security lifecycle services that encompass provisioning, firmware updates, security monitoring, and device identity management. The platform employs a cloud-based architecture, enabling real-time updates and management of security protocols across a fleet of devices. Securyzr iSSP supports Post-Quantum Cryptography standards, ensuring readiness for future cryptographic challenges. This platform integrates seamlessly into diverse system environments, facilitating the protection of sensitive data through robust secure boot processes and key isolation techniques. It structures security around a core Root-of-Trust component named Securyzr iSE neo, which offers anti-tampering protection and dual computation for enhanced security. The platform aligns with an organization's security goals by providing customizable protective measures that are scalable to various applications. Securyzr iSSP is designed to maintain high security levels without compromising system performance or efficiency. By leveraging the latest advancements in cryptography and security protocols, it ensures the resiliency of systems against both physical and remote threats. This platform aids organizations in navigating the increasingly complex landscape of digital security challenges, providing a robust foundation for their cybersecurity strategies.
The AES-XTS standard, as outlined by NIST and IEEE, provides a critical security layer for disk-level data encryption. Through its unique 'tweakable' cipher design, AES-XTS is particularly effective in securing data at rest on disk drives. Helion's AES-XTS solutions are tailored for applications ranging from single drives to extensive storage arrays, offering configurations that balance speed and hardware resource use. With throughput capacities exceeding 64 Gbps, these cores can support both high and low-speed storage applications. Benefiting from Helion's dedication to flexible and efficient designs, these cores ensure consistent data protection across various environments, making them suitable for use in both commercial and industrial sectors. They are available for implementation in leading FPGA and ASIC technologies, ensuring adaptability and integration ease.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
Secure Hash Algorithms (SHA) play a critical role in data integrity and security. The SHA family, including SHA-1, SHA-2, and the widely used SHA-256, provides a method for verifying data through unique hash values that represent original content. Helion Technology designs high-performance and resource-efficient hash cores that cater to both high-speed and low-power applications. Hash functions are integral in digital signatures, message authentication, and integrity verification, ensuring that transmitted or stored data remains unchanged and secure. By aligning the hashing capabilities with robust FPGA and ASIC technologies, Helion offers solutions that enhance data security without imposing hefty resource demands. These cores are engineered for low area and power consumption, making them ideal for compact and energy-sensitive applications.
The Universal DSP Library is designed to simplify digital signal processing tasks. It ensures efficient and highly effective operations by offering a comprehensive suite of algorithms and functions tailored for various DSP applications. The library is engineered for optimal performance and can be easily integrated into FPGA-based designs, making it a versatile tool for any digital signal processing needs. The comprehensive nature of the Universal DSP Library simplifies the development of complex signal processing applications. It includes support for key processing techniques and can significantly reduce the time required to implement and test DSP functionalities. By leveraging this library, developers can achieve high efficiency and performance in their digital signal processing tasks, thereby optimizing overall system resources. Moreover, the DSP library is designed to be compatible with a wide range of FPGAs, providing a flexible and scalable solution. This makes it an ideal choice for developers seeking to create innovative solutions across various applications, ensuring that their designs can handle demanding signal processing requirements effectively.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
aiData is designed to streamline the data pipeline for developing models for Advanced Driver-Assistance Systems and Automated Driving solutions. This automated system provides a comprehensive method of managing and processing data, from collection through curation, annotation, and validation. It significantly reduces the time required for data processing by automating many labor-intensive tasks, enabling teams to focus more on development rather than data preparation. The aiData platform includes sophisticated tools for recording, managing, and annotating data, ensuring accuracy and traceability through all stages of the MLOps workflow. It supports the creation of high-quality training datasets, essential for developing reliable and effective AI models. The platform's capabilities extend beyond basic data processing by offering advanced features such as versioning and metrics analysis, allowing users to track data changes over time and evaluate dataset quality before training. The aiData Recorder feature ensures high-quality data collection tailored to diverse sensor configurations, while the Auto Annotator quickly processes data for a variety of objects using AI algorithms, delivering superior precision levels. These features are complemented by aiData Metrics, which provide valuable insights into dataset completeness and adequacy in covering expected operational domains. With seamless on-premise or cloud deployment options, aiData empowers global automotive teams to collaborate efficiently, offering all necessary tools for a complete data management lifecycle. Its integration versatility supports a wide array of applications, helping improve the speed and effectiveness of deploying ADAS models.
The ultra-low-power human body detector from Microdul is engineered to provide efficient, static detection capabilities essential for wearable technology. This detector helps significantly reduce energy consumption in devices when not actively in use. Its advanced design allows it to recognize the presence or absence of a human, making it ideal for applications requiring power-saving features, such as smart devices and IoT equipment. The precise nature of its operation ensures long battery life, thereby enhancing the user experience in battery-dependent gadgets. Moreover, its application in static detection means it can operate seamlessly without requiring constant recalibration or complex interfacing. Its implementation is particularly valuable in the wearables market where minimizing power draw while maintaining functionality is a critical competitive factor. With its ability to integrate smoothly into existing systems, this detector forms an indispensable part of power-efficient device design strategies focused on long-term effectiveness in changing environments. Its versatility extends to various industries, ensuring compatibility with diverse technological ecosystems while emphasizing seamless operation and reliability. As a result, it paves the way for new possibilities in the design of cutting-edge consumer electronics.
The QUIC Protocol Core by Design Gateway is a high-speed, low-latency communication core designed to optimize network traffic in environments prone to congestion. It offers exceptional performance benefits over traditional protocols, leveraging the latest technology in secure and reliable data transmission.\n\nThis core is engineered to support high-speed environments, enhancing data throughput while reducing the likelihood of packet loss. It is particularly effective in networks with high congestion, where maintaining a seamless and efficient flow of data is critical. The QUIC Protocol Core's design focuses on minimizing latency, providing faster data exchange and enhancing overall network performance.\n\nIntegrating this protocol core into existing network infrastructure supports secure, encrypted data communication, vital for maintaining data integrity across various network environments. Its high-performance capabilities reduce overhead and improve application response times, making it indispensable for modern, high-speed data networks.\n\nBy incorporating the QUIC Protocol Core, businesses can optimize their network capabilities, ensuring secure, efficient, and reliable communications that are crucial for today's technology-driven communication systems.
Specially engineered for the automotive industry, the NA Class IP by Nuclei complies with the stringent ISO26262 functional safety standards. This processor is crafted to handle complex automotive applications, offering flexibility and rigorous safety protocols necessary for mission-critical transportation technologies. Incorporating a range of functional safety features, the NA Class IP is equipped to ensure not only performance but also reliability and safety in high-stakes vehicular environments.
AES-GCM, or AES Galois Counter Mode, combines encryption with authentication to provide both data confidentiality and integrity. Originally developed for high-throughput applications, it can efficiently use pipelining and parallel processing to achieve exceptional speeds. Helion's AES-GCM solutions are tailored to meet diverse data rate requirements, ranging from several megabits to over 40 Gbps. The solutions are versatile across various technologies, offering unparalleled flexibility and performance. Beyond speed, Helion's AES-GCM cores are noted for their compact design, ensuring minimal resource utilization in both FPGA and ASIC implementations. Designed to fit scalable applications, these cores ensure robust data protection in high-demand environments, like networking and data storage.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
The eSi-Crypto suite by EnSilica is a comprehensive collection of cryptographic IP cores designed for both ASIC and FPGA architectures, aiming for minimal resource consumption while ensuring high throughput. A key component within this suite is the True Random Number Generator (TRNG), which adheres to NIST 800-22 standards and is offered as a hard macro in target technologies. Its configurable options are tailored to balance resource efficiency with throughput, making it essential for robust encryption solutions. These IP cores are available as stand-alone modules or integrated with AMBA APB/AHB or AXI bus interfaces.\n\nThe suite supports a variety of cryptographic algorithms such as CRYSTALS Kyber, CRYSTALS Dilithium, elliptic curve cryptography (ECC/ECDSA), RSA, AES, SHA1/SHA2/SHA3, ChaCha20, Poly1305, and TDES/DES. These diverse implementations can be tailored for specific use cases, including high-throughput core configurations ideal for applications like V2X communications. Additionally, the suite's ECC/ECDSA capabilities provide secured digital signature mechanisms, critical for applications requiring stringent data integrity and authenticity.\n\nEnSilica's dedication to cryptographic excellence is further evidenced in their sophisticated handling of secure web-server implementations. By leveraging their ultra-low-power accelerators, particularly for algorithms like ChaCha20 and Poly1305, eSi-Crypto reduces computational overhead while optimizing security performance. This makes the suite a preferred choice for customers seeking efficient and reliable cryptographic solutions across varied technology platforms.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
Designed for high-resolution brain recordings, the Neuropixels Probe is an advanced tool for neuroscience research, offering direct insight into brain activity with unprecedented precision. It enables large-scale data collection across numerous brain regions simultaneously, which is vital for mapping and understanding complex neural circuits. This probe features an array of dense electrodes, making it possible to record from hundreds of neurons at once. Its compact, lightweight design allows for chronic implantation, facilitating long-term brain studies without compromising subject mobility. With its exceptional signal processing capabilities, the probe supports detailed neural data analysis, proving indispensable for neuroscientists aiming to explore new frontiers in brain functionality and disorders. The probe’s integration with CMOS technology ensures high-density data capture with reduced interference and improved accuracy.
The Aeonic Integrated Droop Response System is a groundbreaking approach to managing voltage droop in complex IC environments. This solution combines fast multi-threshold detection with churn-key integration of fine-grained dynamic voltage and frequency scaling capabilities. It offers advanced features such as tight coupling of droop detection and response, leading to the fastest commercial adaptation times that can significantly reduce margin requirements and power usage. The system’s observability features provide valuable data for silicon health assessments and lifecycle management. Process portability ensures scalability across different technology nodes, making the solution versatile for use in various sophisticated systems. This system is crucial for managing droop-induced challenges, and its integration with current architectures leads to enhanced system power and performance efficiency.
The SiFive Essential family provides a comprehensive range of embedded processor cores that can be tailored to various application needs. This series incorporates silicon-proven, pre-defined CPU cores with a focus on scalability and configurability, ranging from simple 32-bit MCUs to advanced 64-bit processors capable of running embedded RTOS and full-fledged operating systems like Linux. SiFive Essential empowers users with the flexibility to customize the design for specific performance, power, and area requirements. The Essential family introduces significant advancements in processing capabilities, allowing users to design processors that meet precise application needs. It features a rich set of options for interface customizations, providing seamless integration into broader SoC designs. Moreover, the family supports an 8-stage pipeline architecture and, in some configurations, offers dual-issue superscalar capabilities for enhanced processing throughput. For applications where security and traceability are crucial, the Essential family includes WorldGuard technology, which ensures comprehensive protection across the entire SoC, safeguarding against unauthorized access. The flexible design opens up various use cases, from IoT devices and microcontrollers to real-time control applications and beyond.
FIPS 140-3 CAVP compliant ultra-fast, compact, and power efficient secure hash acceleration PQPlatform-Hash is a power side-channel accelerator, supporting a wide range of Hash-Based Signature Schemes (HBSS). PQPlatform-Hash deploys tried-and-tested HBSS including quantum-safe LMS and XMSS (not hybrid). It provides acceleration of HBSS in embedded devices, especially where high throughput is required, or resource constraints necessitate minimal additional area. For example, PQPlatform-Hash is a solution for secure first-stage boot loading with hash-based signature schemes. HBSS offer different trade-offs of memory/area to lattice-based schemes, and as a result, PQPlatform-Hash is ideally suited for smaller key sizes, larger signature sizes, and processing times for key generation, signature generation and verification.
OneNav presents the innovative L5-direct GNSS Receiver, a specialized component drawing focus to accuracy and reliability by operating independently of the L1 signal. Leveraging L5 Band signals, this receiver captures and maintains precise location data while ensuring protection against signal jamming. Incorporating a single RF chain, the system reduces redundancy and facilitates optimal antenna placement to enhance device designs in space-restricted environments. This approach critically lowers system costs while delivering robust, reliable location tracking ideal for wearables and IoT applications. The L5-direct receiver integrates seamlessly across multiple satellite constellations like GPS, Galileo, QZSS, and BeiDou, delivering accurate data regardless of environmental constraints. Its refinement in multipath error reduction through machine learning ensures the most precise data acquisition, even in dense urban landscapes. Enhanced with Application Specific Array Processor, the receiver accelerates signal acquisition without sacrificing time or power, ensuring reliable operation wherever used. Additionally, L5-direct GNSS stands out by optimizing power usage, with solutions designed specifically for extended battery life in ultra-low-power devices. Its adaptability allows for integration into diverse systems, serving industries with requirements across different geographies or use cases—from standalone GNSS ASICs to flexible modems and application processors. Featuring silicon-proven capabilities, such as a hot start fix in under one second and open-sky accuracy within 1.5 meters, L5-direct GNSS leads the way for next-generation technology in critical mission deployments.
The NS Class is Nuclei's crucial offering for applications prioritizing security and fintech solutions. This RISC-V CPU IP securely manages IoT environments with its highly customizable and secure architecture. Equipped to support advanced security protocols and functional safety features, the NS Class is particularly suited for payment systems and other fintech applications, ensuring robust protection and reliable operations. Its design follows the RISC-V standards and is accompanied by customizable configuration options tailored to meet specific security requirements.
The FPGA Lock Core is an innovative FPGA solution designed to secure FPGAs and hardware against unauthorized access and counterfeiting, leveraging a Microchip ATSHA204A crypto authentication IC. It reads a unique ID, generates a 256-bit challenge, and uses secure hashing to verify the hardware's authenticity, ensuring hardware integrity in sensitive applications like military and medical fields. This solution allows hardware protection against IP theft by enforcing authentication and disables FPGA functionality if unauthorized access is detected. The core utilizes minimal logic resources and one FPGA pin, communicating through a bidirectional open drain link. The clarity of this system is enhanced by providing the core in VHDL, allowing users to thoroughly understand its functionality, supported by example designs on Cyclone10 and Artix 7 boards, catering to both Intel and Xilinx FPGA platforms. Complementing this security measure is the Key Writer Core, which allows programming of custom secret keys into the ATSHA204A in situ on assembled boards, ensuring a seamless integration with the FPGA Lock system. Available for various FPGA platforms, the Efinix version, distributed with TRS Star, expands its applicability, with webinars and user guides offering in-depth implementation insights.
ArrayNav is at the forefront of GNSS enhancements, utilizing multiple antennas to improve the sensitivity and performance of navigation systems. This sophisticated technology significantly boosts GNSS accuracy in challenging environments such as urban canyons. By leveraging up to four antennas, ArrayNav mitigates multipath issues and strengthens signal reception, dramatically enhancing performance. The heart of ArrayNav's innovation lies in its ability to filter out unwanted signals like interference or jamming attempts, ensuring the precision of GNSS operations. As each antenna adds unique benefits, this system ensures reliable navigation across diverse scenarios, whether in open areas or densely constructed urban landscapes. ArrayNav's technology is pivotal in the automotive sector, especially within advanced driver-assistance systems (ADAS). By providing sharper, more reliable positioning data, it contributes to improved safety and efficiency in vehicular systems, showcasing its indispensable role in modern navigation.
The Advanced Encryption Standard (AES) provides robust encryption for data security applications. Originally chosen by the National Institute of Standards and Technology (NIST) in the late 1990s, AES became the standard for encryption, replacing the older DES system. Helion Technology was at the forefront of this shift, offering a variety of AES IP cores suitable for ASIC and FPGA technologies. Helion's range of AES solutions can address different application needs from minimal area to high-speed data processing. This allows customization and scalability to fit specific encryption requirements. AES includes multiple operational modes, such as CBC, CTR, OFB, and more, enabling users to choose based on throughput and security priorities. With core offerings that cover ultra-low gate count applications to high throughput scenarios, Helion's AES cores are designed to fit seamlessly into a wide range of systems. Furthermore, by embracing process nodes from leading foundry groups, these cores ensure efficient implementation in diverse commercial settings.
The RISC-V Hardware-Assisted Verification by Bluespec is a high-performance platform designed for swift and precise verification of RISC-V cores. It supports testing at both the core level (ISA) and system level, accommodating RTOS and Linux-based environments. This solution can verify standard ISA extensions, custom ISA extensions, and integrated accelerators, making it a versatile tool for various verification needs. One of the standout features of this platform is its scalability and accessibility via the AWS cloud, which ensures that resources can be tapped into as needed, enabling efficient verification anytime, anywhere. Such scalability is crucial for teams that require the flexibility to test various designs without being confined to local server limitations. With an emphasis on broad compatibility, the RISC-V Hardware-Assisted Verification platform is ideal for those involved in developing RISC-V based systems. It assists developers in ensuring their designs are accurate and reliable before deployment, reducing errors and speeding up time-to-market.
The Individual IP Core Modules by ResQuant are comprehensive components engineered to support diverse post-quantum cryptographic standards, including Dilithium, Kyber, XMSS, SPHINCS+, AES, and the SHA-2 family. These modules offer organizations the flexibility to select specific cryptographic functionalities tailored to their security needs, without the necessity of entire systems or hardware changes. Each module is designed to integrate easily into existing infrastructure, ensuring minimal disruption while enhancing security measures against potential future quantum threats. This approach allows industries to gradually implement PQC standards, ensuring a seamless transition to quantum-resistant cryptographic measures. Tailored for flexibility, the ResQuant Individual IP Core Modules can be used across a wide array of applications, from IoT devices to complex military and IT systems. By offering component-level integration, these modules empower companies to future-proof their offerings incrementally while maintaining robust security practices in their operations.
Suite-Q SW is a versatile cryptographic software library designed to offer flexibility in code size, performance, and memory usage, making it an essential tool for developers working on resource-limited devices. Engineered for high adaptability, this software package provides a robust framework for implementing secure cryptographic operations across diverse platforms, including 8-bit to 64-bit processors. The library is meticulously crafted to support various configuration options that balance speed with memory efficiency, ensuring it meets custom specifications while preserving system integrity. Portable C code and high-speed, hand-optimized assembly variants are available to provide the ideal blend of compatibility and performance required in modern applications. Key features of Suite-Q SW include seamless integration as plug-in modules, support for a wide range of hardware offloads, and extensive compatibility with general-purpose and embedded CPUs. Validated through rigorous testing and performance measurements, it provides a reliable basis for secure software development, ensuring rapid deployment with minimized risk. As such, Suite-Q SW remains an indispensable part of PQSecure's comprehensive cryptographic offerings, perfect for adapting to the ever-changing landscape of digital security.
Belonging to the AONSensâ„¢ Neural Network series, the AON1020 is crafted for both voice and audio recognition alongside other sensor applications. Recognized for its hectic performance in minimal power environments, AON1020's AI processing engine is available in Verilog RTL, making it accessible for use in ASIC and FPGA technologies. Engineered for scenarios like human activity detection through sensor applications, this IP provides always-on multi-wake-word detection and on-device voice command recognition. Its features ensure adaptability even in environments characterized by noise, offering stable performance irrespective of user or environmental changes. The AON1020's robust architecture accommodates sensor fusion applications, enhancing its capability in multi-sensor environments where it can decipher activities like running or walking. This offers developers potent solutions in expanding markets such as smart home automation and industrial IoT applications.
The NI Class RISC-V CPU IP caters to communication, video processing, and AI applications, providing a balanced architecture for intensive data handling and processing capabilities. With a focus on high efficiency and flexibility, this processor supports advanced data crunching and networking applications, ensuring that systems run smoothly and efficiently even when managing complex algorithms. The NI Class upholds Nuclei's commitment to providing versatile solutions in the evolving tech landscape.
Suite-Q HW is a robust system-on-chip (SoC) solution that envelops all the necessary cryptography required for secure protocols within compact and efficient hardware. Targeted at both high-end servers and low-end embedded systems, this solution emphasizes the dual benefits of scalability and adaptability. Suite-Q HW efficiently offloads demanding symmetric and asymmetric cryptographic processes by leveraging specialized accelerators, offering enhanced execution speeds that cater to different application requirements. A key component of its utility lies in its support for a wide array of cryptographic operations. This includes classical public key methods, such as ECDSA and ECDH, alongside emerging post-quantum techniques within isogeny and lattice frameworks. The hardware is further augmented by secure hash algorithms and diverse AES encryption modes, delivering comprehensive protection across a variable security landscape. Incorporating optional Differential Power Analysis (DPA) countermeasures and validated security standards, Suite-Q HW ensures security for sensitive data against contemporary and emerging threats. It facilitates integration with existing development flows across SoCs and FPGAs, optimizing power and silicon footprint according to specific needs. Furthermore, the hardware package provides comprehensive resources for integration, from testbench data to simulation scripts, enhancing its adaptability and effectiveness in today's digital security paradigm.
FIPS 140-3 CMVP compliant, CAVP PQC cryptographic library designed for PQ/T Hybrid PQCryptoLib is a general-purpose FIPS 140-3 CMVP and CAVP-certified cryptographic library. It’s been designed for a wide variety of applications and provides the latest NIST-standardized post-quantum and classical algorithms in a software environment. With a configurable, secure, and easy-to-use API, PQCryptoLib is optimized for crypto-agility, particularly when it comes to FIPS-compliant hybrid PQ/T solutions, and with crypto-agility in mind, it’s built to protect against the threat of ‘harvest-now-decrypt-later’ attacks. The aim of PQCryptoLib is to help organizations transition smoothly and securely to quantum resistance in a manageable, easy-to-integrate solution.
The JPEG-LS Encoder by Parretto B.V. is a lossless image compression solution for FPGA applications, renowned for its adherence to the JPEG-LS standard. This encoder excels in lossless scenarios, outperforming the JPEG-2000 in resource efficiency while requiring neither external memory nor complicated setup, resulting in lower latency. This IP-core is perfect for applications where high-quality, lossless image compression is essential, catering to image depths from 8 to 16 bits. It processes one pixel per clock cycle, ensuring smooth and efficient compression workflows. With configurable output data width and the ability to manage ultra-high-definition image sizes, it's a versatile choice for a variety of imaging needs. Typically used in applications requiring pristine image fidelity, the JPEG-LS Encoder supports pixel and data FIFO interfaces alongside Avalon streaming for data handling flexibility. Developers can trust its performance for critical tasks where low-latency and high-quality compression are paramount, making it a foundational tool in modern image processing systems.
The AES Core by Algotronix is a sophisticated solution tailored for securing data using advanced encryption methods. This core supports various encryption modes such as ECB, CBC, CTR, CFB, OFB, CCM, GCM, and XTS, which cater to a wide array of applications requiring different levels and methods of data protection. The flexibility in supported modes allows for tailored implementations in different security-critical environments. This encryption core is known for its deployment among prominent defense electronics organizations, and it has been operational within several NATO member states, testifying to its high-level security assurance and operational readiness in sensitive global contexts. Offered typically in source code form, the AES Core ensures that users can perform thorough security audits and tailor enhancements specific to their security policies and infrastructural needs. This capability positions Algotronix's offering as an optimal choice for organizations prioritizing stringent security postures.
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