All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
Akida's Neural Processor IP represents a leap in AI architecture design, tailored to provide exceptional energy efficiency and processing speed for an array of edge computing tasks. At its core, the processor mimics the synaptic activity of the human brain, efficiently executing tasks that demand high-speed computation and minimal power usage. This processor is equipped with configurable neural nodes capable of supporting innovative AI frameworks such as convolutional and fully-connected neural network processes. Each node accommodates a range of MAC operations, enhancing scalability from basic to complex deployment requirements. This scalability enables the development of lightweight AI solutions suited for consumer electronics as well as robust systems for industrial use. Onboard features like event-based processing and low-latency data communication significantly decrease the strain on host processors, enabling faster and more autonomous system responses. Akida's versatile functionality and ability to learn on the fly make it a cornerstone for next-generation technology solutions that aim to blend cognitive computing with practical, real-world applications.
The second-generation Akida platform builds upon the foundation of its predecessor with enhanced computational capabilities and increased flexibility for a broader range of AI and machine learning applications. This version supports 8-bit weights and activations in addition to the flexible 4- and 1-bit operations, making it a versatile solution for high-performance AI tasks. Akida 2 introduces support for programmable activation functions and skip connections, further enhancing the efficiency of neural network operations. These capabilities are particularly advantageous for implementing sophisticated machine learning models that require complex, interconnected processing layers. The platform also features support for Spatio-Temporal and Temporal Event-Based Neural Networks, advancing its application in real-time, on-device AI scenarios. Built as a silicon-proven, fully digital neuromorphic solution, Akida 2 is designed to integrate seamlessly with various microcontrollers and application processors. Its highly configurable architecture offers post-silicon flexibility, making it an ideal choice for developers looking to tailor AI processing to specific application needs. Whether for low-latency video processing, real-time sensor data analysis, or interactive voice recognition, Akida 2 provides a robust platform for next-generation AI developments.
**Ceva-Waves Links** is a growing family of multi-standard wireless platforms. By optimizing connectivity support for various combinations of **Wi-Fi, Bluetooth, 802.15.4, and ultra-wideband (UWB)**, the Ceva-Waves Links family provides preconfigured, optimized solutions for SoCs requiring multiple connectivity standards. All Ceva-Waves Links configurations are based on field-proven Ceva-Waves hardware IP and software stacks. Unique Ceva coexistence algorithms ensure efficient and interference-free operation of multiple connections while sharing one radio. The **Ceva-Waves Links family** offers combinations of Ceva-Waves Wi-Fi, Ceva-Waves Bluetooth, 802.15.4 (supporting protocols such as Thread, Matter and Zigbee), and Ceva-Waves UWB hardware IP, integrated with Ceva or third-party radios and CPU- and OS-agnostic software stacks. New platforms will be introduced to address market trends or customers’ demands. [**Learn more about Ceva-Waves Links family solution>**](https://www.ceva-ip.com/product/ceva-waves-links/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_links_page)
**Ceva-XC21** is the most efficient vector DSP core available today for communications applications. The Ceva-XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications. Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices. Targeted for 5G and 5G-Advanced workloads, the Ceva-XC21 has multiple products configurations enabling system designers to optimize the size and cost to their specific application needs. The Ceva-XC21, based on the advanced Ceva-XC20 architecture, features a product line of 3 vector DSP cores. Each of the cores offers a unique performance & area configuration with a SW compatibility between them. The different cores span across single thread or dual thread configurations, and 32 or 64 16bits x 16bits MACs. The Ceva-XC212, the highest performing variant of the Ceva-XC21 delivers up to 1.8x times the performance of Ceva’s previous-generation Ceva-XC4500 architecture, while reducing the core area. Ceva-XC210, the smallest configuration of the Ceva-XC21, enables system designers to reduce the core die size in 48% compared with the previous generation. Ceva-XC211 offers the same performance envelope compared with the previous generation at 63% of the area. [**Learn more about Ceva-XC21>**](https://www.ceva-ip.com/product/ceva-xc21/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_xc21_page)
The **Ceva-Waves Bluetooth platform** includes field-proven hardware IP for baseband controller, modem, and 2.4 GHz RF transceiver functions, and allows use of many third-party radio IPs as well. The platform includes optimized baseband controller hardware and software, and above the Host Controller Interface (HCI) a host-agnostic software protocol stack supporting all major Bluetooth profiles. The built-in 802.15.4 add-on suite shares the same Bluetooth radio, and includes IEEE 802.15.4 MAC & modem hardware IP and software, and is compatible with Zigbee, Thread and Matter host protocol stacks. The Ceva-Waves Bluetooth platform is also available as part of the **Ceva-Waves Links family** of multi-protocol turnkey platforms, including with optimized Wi-Fi & Bluetooth co-existence interface and packet traffic arbiter. The Ceva-Waves Bluetooth platforms also comprises a state-of-the-art radio in TSMC 12nm FFC+ supporting all the latest Bluetooth 6.0 dual mode features, along with next gen Bluetooth High Data Throughput and IEEE 802.15.4. Its innovative architecture provides best in class performance in term of power consumption, die size, sensitivity and output power. [**Learn more about Ceva's Bluetooth solution>**](https://www.ceva-ip.com/product/ceva-waves-bluetooth/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_bluetooth_page)
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
**Ceva-Waves UWB platform** cuts the development time and risk for implementing a wide range of UWB functionality in SoCs. It provides optimized MAC and PHY hardware IP and supporting software for secure and accurate ranging, and Doppler Radar presence detection applications. It can be implemented in an SoC independently or in conjunction with the Ceva-Waves Bluetooth platform, as well as part of the Ceva-Waves Links family of multiprotocol platforms. The Ceva-Waves UWB platform includes hardware IP for an optimized UWB MAC and PHY meeting 802.15.4 HRP, FiRa 3.0, and the Car Connectivity Consortium Digital Key 3.0 (CCC DK3.0) requirements. The platform includes advanced Wi-Fi interference suppression. A comprehensive suite of CPU-agnostic software stacks that support FiRa 3.0 MAC, CCC DK3.0 MAC, and radar for implementing applications such as automotive digital keys and in-cabin child-presence detection (CPD), general power-saving presence detection in laptops, TVs and smart buildings, asset tracking tags, real-time location services (RTLS), and tap-free payment. [**Learn more about our UWB soluion>**](https://www.ceva-ip.com/product/ceva-waves-uwb/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_uwb_page)
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
**Ceva-Waves Dragonfly platform** is a turnkey platform with optimized, low-power hardware IP and protocol software for implementing narrow-band IoT (NB-IoT) cellular modem SoCs. Extensions provide support for GNSS such as GPS and BeiDou and for sensor-fusion applications. The Ceva-Waves Dragonfly platform comprises hardware IP with an enhanced Ceva-BX1 processor, specific hardware accelerators, and SoC infrastructure IP. Software includes NB-IoT protocol stack for L1 through L3 functions including encryption and software PHY, a task-optimized RTOS, and optional GNSS receiver and control software, all executing on the Ceva-BX1. Pre-certified for 3GPP Release 15 CAT NB2, the solution is tuned for small footprint and extremely low power, yet has headroom for additional software-defined functions, such as sensor fusion. [**Learn more about Ceva-Waves Dragonfly>**](https://www.ceva-ip.com/product/ceva-waves-dragonfly/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_dragonfly_page)
The ARINC 818 Product Suite by Great River Technology provides a comprehensive solution for high-performance digital video transmission in avionics applications. It supports the implementation, qualification, testing, and simulation of ARINC 818 products. This suite allows developers to access essential ARINC 818 tools and resources. It ensures optimal performance and reliability in mission-critical equipment by offering both hardware and software components tailored for the ARINC 818 standard. With its focus on high-speed data transfer and signal integrity, the ARINC 818 Product Suite is ideal for applications requiring lossless video transmission and real-time data handling in challenging conditions.
The EW6181 is an advanced multi-GNSS silicon solution designed for high sensitivity and precision. This powerful chip supports GPS, Glonass, BeiDou, Galileo, SBAS, and A-GNSS, offering integration flexibility with various applications. Its built-in RF frontend and digital baseband facilitate robust signal processing, controlled by an ARM MCU. The EW6181 integrates essential interfaces for diverse connectivity, matched with DC-DC converters and LDOs to minimize BOM in battery-driven setups. This silicon marries low power demands with strong functional capabilities, thanks to proprietary algorithms that optimize its operation. It’s engineered to deliver exceptional accuracy and sensitivity in both standalone and cloud-related environments, adapting smoothly to connected ecosystems for enhanced efficiency. Its compact silicon footprint further enhances its suitability for applications needing prolonged battery life and reliable positioning. With a focus on Antenna Diversity, the EW6181 shines in dynamic applications like action cameras and smartwatches, ensuring clear signal reception even when devices rapidly rotate. This aspect accentuates the chip's ability to maintain consistent performance across a range of challenging environments, reinforcing its role in the forefront of GNSS technology.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
**Ceva-Waves Wi-Fi platforms portfolio** provide a comprehensive selection of hardware IP and CPU-agnostic host software for energy-efficient SoC implementation of any of a wide range of Wi-Fi subsystems, from Wi-Fi 4 to Wi-Fi 7, for both client devices and access points. The portfolio includes a suite of pre-optimized solutions for various generations and configurations for specific Wi-Fi uses, power consumption levels, and price points, ranging from low-bandwidth IoT connectivity to high-bandwidth hubs. Embedded into one of the Ceva-Waves Links multi-protocol wireless platforms, the Ceva-Waves Wi-Fi IPs can efficiently co-exist with the Ceva-Waves Bluetooth IPs and/or Ceva-Waves UWB IP. The Ceva-Waves Wi-Fi platforms comprise hardware modem PHY IP that supports DSSS, CCK, OFDM and OFDMA modulations; optimized MAC IP that offloads MAC functions from the CPU; and a comprehensive selection of MAC protocol software stacks. The IP and software elements are further organized into three main solution profiles. * Wi-Fi IoT is for energy-efficient low-bandwidth connectivity for IoT devices, supporting 2.4GHz single band or dual/triple bands on 2.4/5/6 GHz for IEEE 802.11n, ax, or be (Wi-Fi 4, 6 or 7). * Wi-Fi High-Performance supports up to 160 MHz bands at 2.4, 5, or 6 GHz in either single-antenna or 2×2 MIMO mode for IEEE 802.11ax or be (Wi-Fi 6 or 7), and is intended for consumer media-streaming applications. * Wi-Fi Access Point supports 160 MHz bands and 2×2 MIMO for IEEE 802.11ax or be (Wi-Fi 6/6E/7), for applications such as media access points, gateways, and small-cell offload that must support up to hundreds of clients. The Ceva-Waves Wi-Fi platforms include a coexistence interface that permits highly efficient operation with the Ceva-Waves Bluetooth platforms. [**Learn more about Ceva-Waves Wi-Fi solution>**](https://www.ceva-ip.com/product/ceva-waves-wi-fi/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_wifi_page)
aiSim 5 is a state-of-the-art automotive simulation platform designed for ADAS and autonomous driving testing. Recognized as the world's first ISO26262 ASIL-D certified simulator, it offers unparalleled accuracy and determinism in simulating various driving scenarios and environmental conditions. The simulator integrates AI-based digital twin technology and an advanced rendering engine to create realistic traffic scenarios, helping engineers verify and validate driver assistance systems. Harnessing powerful physics-based simulation capabilities, aiSim 5 replicates real-world phenomena like weather effects and complex traffic dynamics with precision. By offering a comprehensive set of 3D assets and scenarios, it allows for the extensive testing of systems in both typical and edge conditions. With its flexible and open architecture, aiSim 5 can seamlessly integrate into existing testing toolchains, supporting significant variations in sensor configurations and driving algorithms. The platform encourages innovation in simulation methodologies by providing tools for scenario randomization and synthetic data generation, crucial for developing resilient ADAS applications. Additionally, its cloud-ready architecture makes it applicable across various hardware platforms, turning simulation into a versatile resource available on inexpensive or high-end computing configurations alike.
The Digital PreDistortion (DPD) Solution offered by Systems4Silicon is a versatile technology aimed at significantly enhancing the efficiency of RF power amplifiers. This advanced sub-system is scalable and adaptable to both ASIC and FPGA platforms, ensuring broad compatibility across various device vendors. The DPD solution meticulously enhances linearity, crucial for devices operating within multi-standard environments, such as 5G and O-RAN systems.\n\nDesigned to optimize the signal processing in transmission systems, this DPD technology allows for considerable power savings by enabling amplifiers to function more efficiently. Systems4Silicon’s approach ensures that the system can maintain its performance across different transmission bandwidths, which can scale to 1 GHz or higher. This makes it particularly valuable for large-scale and high-frequency applications.\n\nThe DPD technology's implementation is straightforward, providing a field-proven solution that integrates seamlessly with current infrastructures. Its adaptability is not merely limited to the hardware spectrum but extends to accommodate evolving communication standards, ensuring it remains relevant and effective in diverse market scenarios.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
The HOTLink II Product Suite by Great River Technology is tailored for mission-critical avionics systems requiring robust data communication. It enables seamless data transfer and ensures consistent performance under high-stress operational environments. This suite incorporates advanced technologies to handle complex data streams effectively. It includes component options that enhance data throughput and communication efficiency, meeting stringent industry standards for avionics platforms. Designed with precision, the HOTLink II suite supports the integration and management of large datasets, ensuring that avionics systems can perform efficiently and reliably, crucial for modern aircraft and defense applications.
The CANmodule-III is a sophisticated full CAN controller designed to handle communication on the CAN bus with outstanding efficiency. Built upon Bosch's fundamental CAN architecture, this module is fully CAN 2.0B compliant, facilitating seamless communication transactions across the network. It is optimized for system-on-chip integrations, providing customizable options to cater to specific application requirements. The module stands out with its inherited functions which ensure uninterrupted main core operations, even when additional functionalities are layered around it. Having been deployed in various applications from aerospace to industrial control, the CANmodule-III's proven reliability makes it a preferred choice for developers seeking robust communication solutions in FPGA and ASIC technologies.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Ncore Cache Coherent Interconnect is designed to tackle the multifaceted challenges in multicore SoC systems by introducing heterogeneous coherence and efficient cache management. This NoC IP optimizes performance by ensuring high throughput and reliable data transmission across multiple cores, making it indispensable for sophisticated computing tasks. Leveraging advanced cache coherency, Ncore maintains data integrity, crucial for maintaining system stability and efficiency in operations involving heavy computational loads. With its ISO26262 support, it caters to automotive and industrial applications requiring high reliability and safety standards. This interconnect technology pairs well with diverse processor architectures and supports an array of protocols, providing seamless integration into existing systems. It enables a coherent and connected multicore environment, enhancing the performance of high-stakes applications across various industry verticals, from automotive to advanced computing environments.
This mmWave PLL is engineered to deliver exceptional performance in high-frequency applications, such as mmWave communications and advanced radar systems. The IP offers remarkable frequency synthesis capabilities, essential for the operation of modern communication networks and sensors, including the growing 5G infrastructure and automotive radar technologies. The design incorporates mechanisms to optimize phase noise and enhance frequency stability, which are critical in minimizing signal distortion in high-bandwidth transmissions. This PLL is compact yet powerful, making it an excellent choice for systems where space and performance are at a premium. Suitable for integration into a variety of RF and mmWave architectures, the mmWave PLL supports applications across telecommunications, automotive, and beyond. It helps designers achieve superior system performance while maintaining low latency and high data throughput.
The TW330 distortion correction IP is tailored for use in applications requiring dynamic image transformations, such as VR headsets and automotive HUDs. Utilizing GPU-powered technologies, it offers real-time coordinate transformations, distortion corrections, and other modifications up to a resolution of 16K x 16K in both RGB and YUV formats. This IP is crucial for enhancing visual accuracy and display adaptability across varied markets.
Designed for seamless integration, High PHY Accelerators from AccelerComm encapsulate top-tier signal processing blocks critical for 5G solutions. Available as FPGA and ASIC ready IP cores, they are tailored for rapid deployment with minimal risk. These accelerators are supported by accurate simulation models and designed to use standardized interfaces for integration. Notably, they also provide support for space-hardened platforms, ensuring robust performance in diverse settings.
The AST 500 and AST GNSS-RF are multifaceted SOC and RF solutions designed for GNSS applications. They support a wide array of constellations such as GPS, GLONASS, NavIC, and others, in multiple frequency bands, enhancing navigation performance. These ICs integrate features like secure boots and data encryption, facilitating robust security measures crucial for sensitive data. The AST GNSS-RF is equipped with capabilities for L1, L2, L5, and S band reception, catering to high-fidelity signal requirements across various applications. The support for dual-band reception ensures that ionosphere errors are minimized, offering exceptional positioning accuracy.
Polar ID from Metalenz offers a cutting-edge face unlock solution, using advanced meta-optic technology to provide secure, high-resolution facial recognition capabilities. It captures the unique "polarization signature" of a human face, making it resistant to both 2D photos and sophisticated 3D masks. Polar ID operates efficiently in a variety of lighting conditions, from bright daylight to dark environments, ensuring its utility extends across all smartphone models without sacrificing security or user experience. This technology replaces complex structured light modules, incorporating a single near-infrared polarization camera and active illumination source. It significantly reduces costs and footprint, supporting a broad adoption across hundreds of millions of mobile devices. With its low price point and high performance, Polar ID elevates smartphone security, offering robust protection for digital transactions and identity verification. By enabling this on an embedded platform with compatibility for Qualcomm's Snapdragon processors, Metalenz ensures widespread applicability. The key advantage of Polar ID is its affordability and ease of integration, as it eliminates the need for larger, more intrusive notches in phone designs. Its sophisticated polarization sensing means secure authentication is possible even if the user wears sunglasses or masks. Polar ID sets a new benchmark in smartphone security by delivering convenience and enhanced protection, marking it as the first polarization sensor available for smartphones.
The RISCV SoC developed by Dyumnin Semiconductors is engineered with a 64-bit quad-core server-class RISCV CPU, aiming to bridge various application needs with an integrated, holistic system design. Each subsystem of this SoC, from AI/ML capabilities to automotive and multimedia functionalities, is constructed to deliver optimal performance and streamlined operations. Designed as a reference model, this SoC enables quick adaptation and deployment, significantly reducing the time-to-market for clients. The AI Accelerator subsystem enhances AI operations with its collaboration of a custom central processing unit, intertwined with a specialized tensor flow unit. In the multimedia domain, the SoC boasts integration capabilities for HDMI, Display Port, MIPI, and other advanced graphic and audio technologies, ensuring versatile application across various multimedia requirements. Memory handling is another strength of this SoC, with support for protocols ranging from DDR and MMC to more advanced interfaces like ONFI and SD/SDIO, ensuring seamless connectivity with a wide array of memory modules. Moreover, the communication subsystem encompasses a broad spectrum of connectivity protocols, including PCIe, Ethernet, USB, and SPI, crafting an all-rounded solution for modern communication challenges. The automotive subsystem, offering CAN and CAN-FD protocols, further extends its utility into automotive connectivity.
AccelerComm’s LDPC solutions cater specifically to the 5G standards, offering high efficiency and leading performance in channel coding. The IP suite includes comprehensive encoder and decoder capabilities that enhance hardware efficiency for this critical component of the PHY layer. This facilitates a marked improvement in throughput and error reduction, aligning with 3GPP standards. Born from academic excellence at Southampton University, they incorporate cutting-edge algorithms for signal performance, achieving substantial decoder performance enhancement and minimizing error floors.
Packetcraft's Bluetooth LE Audio Solutions offer a full suite of host, controller, and LC3 components optimized for seamless transition to Bluetooth LE Audio. The platform supports Auracast broadcast audio and True Wireless Stereo (TWS), making it adaptable to prevalent chipsets and providing flexibility to product companies. The modular design facilitates simplified integration, ensuring companies can leverage advanced audio capabilities in a variety of applications. As Bluetooth audio technology evolves, Packetcraft remains at the leading edge, offering industry-leading solutions that cater to modern audio requirements.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
LightningBlu is a state-of-the-art multi-gigabit connectivity solution for high-speed rail networks, delivering continuous high-speed data transfer between trackside and train systems. This innovative solution works within the mmWave spectrum of 57-71 GHz and is certified for long-term, low-maintenance deployment. It seamlessly integrates with existing trackside networks to provide a stable, high-capacity communication bridge essential for internet access, entertainment, and real-time information services aboard high-speed trains. The LightningBlu system includes robust trackside nodes and compact train-top nodes designed for seamless installation, significantly enhancing operational efficiencies and passenger experience by providing internet speeds superior to traditional mobile broadband services. With aggregate throughputs reaching around 3 Gbps, LightningBlu sets the standard for rail communications by supporting speeds at which data demands are met with ease. Crucially, LightningBlu is a key component in transforming the railway telecommunications landscape, offering upgraded technology that enables uninterrupted and enhanced passenger digital services even in the busiest railways across the UK and USA. Through its advanced mmWave technology, it ensures that the connectivity needs of the modern commuter are met consistently and effectively, paving the way for a new era in transit communication.
The ORC3990 is a groundbreaking LEO Satellite Endpoint SoC engineered for use in the Totum DMSS Network, offering exceptional sensor-to-satellite connectivity. This SoC operates within the ISM band and features advanced RF transceiver technology, power amplifiers, ARM CPUs, and embedded memory. It boasts a superior link budget that facilitates indoor signal coverage. Designed with advanced power management capabilities, the ORC3990 supports over a decade of battery life, significantly reducing maintenance requirements. Its industrial temperature range of -40 to +85 degrees Celsius ensures stable performance in various environmental conditions. The compact design of the ORC3990 fits seamlessly into any orientation, further enhancing its ease of use. The SoC's innovative architecture eliminates the need for additional GNSS chips, achieving precise location fixes within 20 meters. This capability, combined with its global LEO satellite coverage, makes the ORC3990 a highly attractive solution for asset tracking and other IoT applications where traditional terrestrial networks fall short.
The 802.11ah HaLow transceiver is designed to provide efficient and reliable connectivity for IoT devices, utilizing sub-GHz frequencies to ensure long-range transmission while maintaining minimal power consumption. This transceiver is a perfect fit for environments where traditional Wi-Fi bands fall short due to range or power constraints. Offering superior penetration through obstacles and walls, this transceiver is ideally suited for industrial IoT, smart agriculture, and connected home systems. Its long-range capabilities make it especially useful in applications requiring broad coverage across expansive areas or dense urban settings. Beyond range enhancements, the 802.11ah HaLow standard supported by this transceiver allows for interoperability with various IoT ecosystems, simplifying device integration and promoting scalability. By balancing power efficiency and connectivity, it supports seamless operation for battery-operated devices, aiding in the creation of sustainable IoT networks.
aiData is designed to streamline the data pipeline for developing models for Advanced Driver-Assistance Systems and Automated Driving solutions. This automated system provides a comprehensive method of managing and processing data, from collection through curation, annotation, and validation. It significantly reduces the time required for data processing by automating many labor-intensive tasks, enabling teams to focus more on development rather than data preparation. The aiData platform includes sophisticated tools for recording, managing, and annotating data, ensuring accuracy and traceability through all stages of the MLOps workflow. It supports the creation of high-quality training datasets, essential for developing reliable and effective AI models. The platform's capabilities extend beyond basic data processing by offering advanced features such as versioning and metrics analysis, allowing users to track data changes over time and evaluate dataset quality before training. The aiData Recorder feature ensures high-quality data collection tailored to diverse sensor configurations, while the Auto Annotator quickly processes data for a variety of objects using AI algorithms, delivering superior precision levels. These features are complemented by aiData Metrics, which provide valuable insights into dataset completeness and adequacy in covering expected operational domains. With seamless on-premise or cloud deployment options, aiData empowers global automotive teams to collaborate efficiently, offering all necessary tools for a complete data management lifecycle. Its integration versatility supports a wide array of applications, helping improve the speed and effectiveness of deploying ADAS models.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The RWM6050 Baseband Modem is an innovative component of Blu Wireless's mmWave technology portfolio, architected to support high-bandwidth, high-capacity data communications. Designed in collaboration with industry leaders Renesas, this modem unit stands out for its efficiency and versatility, effectively marrying physical modem layers with advanced processing capabilities. The RWM6050 modem is instrumental in providing seamless data transmission for access and backhaul networks. Built to accommodate varying channelisation modes, the RWM6050 supports deep levels of customisation for different bandwidth requirements and transmission distances. It handles multi-gigabit throughput, which makes it ideal for expanding connectivity in urban or industrial areas with dense infrastructure requirements. From smart cities to complex transport systems, this baseband modem scales effectively to meet demanding data needs. Equipped with dual modems and integrated mixed-signal front-end capabilities, the RWM6050 offers a flexible solution for evolving communication infrastructures. Its design ensures optimization for real-time digital signal processing, beamforming, and adaptable connectivity management. The RWM6050 is a key enabler in unlocking the full potential of mmWave technology in a variety of settings, furthering connectivity innovations.
The FCM1401 is a 14GHz CMOS Power Amplifier tailored for Ku-band applications, operating over a frequency range of 12.4 to 16 GHz. This amplifier exhibits a gain of 22 dB and a saturated output power (Psat) of 19.24 dBm, ensuring optimal performance with a power-added efficiency (PAE) of 47%. The architecture enables reduction in battery consumption and heat output, making it ideal for satellite and telecom applications. Its small silicon footprint facilitates integration in space-constrained environments.
The Hyperspectral Imaging System offers advanced solutions for capturing detailed spectral information beyond the visible range. This system provides unmatched access to spectral imaging, making it ideal for applications requiring precise detail, such as environmental monitoring and industrial inspection. Hyperspectral imaging divides the spectrum into many bands, delivering a richer data set that enhances material identification, classification, and analysis. This technology is pivotal where high precision in spectral analysis is necessary, aiding sectors such as agriculture and defense. Capable of capturing spectral data in high resolution across multiple wavelengths, the system's applications extend to medical fields, offering improved diagnostics and insights into biological samples. Integrating state-of-the-art CMOS technology, it ensures fast, accurate data acquisition with lower power consumption.
TES Electronic Solutions provides a comprehensive Ultra-Wideband (UWB) technology suite tailored for high-precision ranging and communication applications. UWB Technology & IP is designed to offer robust wireless data transmission, combining low power consumption with high data rates, ideal for indoor positioning and real-time location tracking systems. The UWB solutions support various industrial standards, ensuring interoperability across different platforms and systems, which is essential for modern interconnected environments. With its strong signal resilience and multipath immunity, UWB Technology & IP is particularly effective in environments with reflective materials or where traditional wireless technologies might struggle. This technology is vital in applications requiring precision, such as asset tracking, position monitoring, and security systems. TES's framework ensures flexibility, allowing for customization and optimization based on unique client requirements, facilitating integration into existing and future communication infrastructures.
The Polar channel coding offering by AccelerComm is crafted for the 3GPP 5G NR, providing both uplink and downlink encoding and decoding capabilities. Designed for easy integration, it includes PC- and CRC-aided SCL polar decoding techniques to ensure uncompromised error correction. Key parameters of the decoding IP can be tuned to adjust parallelism, latency, and throughput, making it adaptable to specific application needs without sacrificing performance.
ZIA Image Signal Processing technology provides state-of-the-art solutions for optimizing image quality and enhancing vision-based systems. This technology is integral to applications requiring precise image analysis, such as surveillance cameras and automotive safety systems. It supports various image processing tasks, including de-noising, color correction, and sharpness enhancement, delivering superior visual output even under challenging conditions. ZIA's adaptable architecture supports integration into a range of devices, ensuring broad applicability across multiple sectors.
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications. It features layered decoding, soft decision decoding, and is compliant with IEEE 802.11n/ac/ax standards. The decoder supports all LDPC code rates of ½, ⅔, ¾, and ⅚, as well as all LDPC codeword sizes of 648, 1296, and 1944 bits. This IP provides a high throughput design and allows for frame-to-frame on-the-fly configuration, offering configurable LDPC decoding iterations for a trade-off between throughput and error correction performance.
The RFicient chip is designed for the Internet of Things (IoT) applications, famously recognized for its ultra-low-power operations. It aims to innovate the IoT landscape by offering a highly efficient receiver technology that significantly reduces power consumption. This chip supports energy harvesting to ensure sustainable operation and contributes to green IoT development by lessening the dependency on traditional power sources. Functionally, the RFicient chip enhances IoT devices' performance by providing cutting-edge reception capabilities, which allow for the consistent and reliable transmission of data across varied environments. This robustness makes it ideal for applications in industrial IoT settings, including smart cities and agricultural monitoring, where data integrity and longevity are crucial. Technically advanced, the RFicient chip's architecture employs intelligent design strategies that leverage low-latency responses in data processing, making it responsive and adaptable to rapid changes in its operational environment. These characteristics position it as a versatile solution for businesses aiming to deploy IoT networks with minimal environmental footprint and extended operational lifespan.
The VoSPI Rx for FLIR Lepton IR Sensor is designed to cater to infrared sensor needs for various applications. Specially configured to support the FLIR Lepton sensor, this receiver facilitates effective and precise data handling of infrared signals, crucial in environments demanding high thermal accuracy. It provides real-time processing capabilities, aligning with the rigorous demands of security and monitoring applications. This receiver excels in maintaining data integrity, ensuring that the thermal data transmitted across platforms is of the highest accuracy. Its sophisticated engineering allows it to work seamlessly with other system components, enhancing system performance and reliability. The receiver is integrated with features that boost signal processing while minimizing latency, providing a seamless operational environment. This ensures that users can rely on it for consistent performance across various industry applications, boosting both efficiency and reliability.
The transceiver is designed to be used together with an RF tuner, and ADC/DAC converters. The system has internal state machine to control the operation, and can be externally configured via the SPI interface. This design is a Mobile WiMAX baseband transceiver core for both Base station and Mobile station, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner. The operation of the transceiver is automated by a master finite state machine.
OneNav presents the innovative L5-direct GNSS Receiver, a specialized component drawing focus to accuracy and reliability by operating independently of the L1 signal. Leveraging L5 Band signals, this receiver captures and maintains precise location data while ensuring protection against signal jamming. Incorporating a single RF chain, the system reduces redundancy and facilitates optimal antenna placement to enhance device designs in space-restricted environments. This approach critically lowers system costs while delivering robust, reliable location tracking ideal for wearables and IoT applications. The L5-direct receiver integrates seamlessly across multiple satellite constellations like GPS, Galileo, QZSS, and BeiDou, delivering accurate data regardless of environmental constraints. Its refinement in multipath error reduction through machine learning ensures the most precise data acquisition, even in dense urban landscapes. Enhanced with Application Specific Array Processor, the receiver accelerates signal acquisition without sacrificing time or power, ensuring reliable operation wherever used. Additionally, L5-direct GNSS stands out by optimizing power usage, with solutions designed specifically for extended battery life in ultra-low-power devices. Its adaptability allows for integration into diverse systems, serving industries with requirements across different geographies or use cases—from standalone GNSS ASICs to flexible modems and application processors. Featuring silicon-proven capabilities, such as a hot start fix in under one second and open-sky accuracy within 1.5 meters, L5-direct GNSS leads the way for next-generation technology in critical mission deployments.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Wasiela's LTE Lite offers a streamlined solution for LTE communications by supporting user equipment (UE) compliant with Category 0/1 standards. It integrates seamlessly with intermediate frequency (IF) inputs and accommodates various channel bandwidth configurations, including 1.4, 3, 5, 10, 15, and 20 MHz. This flexibility is key for devices with varying broadband requirements, enabling efficient transmission across different frequency bands. The LTE Lite solution is engineered to optimize modulation processes, supporting Quadrature Phase Shift Keying (QPSK) and higher-order QAM options. This allows it to adapt to diverse telecommunication needs by balancing between data rate and signal strength, achieving optimal performance in both high and low signal environments. Built to be resource-efficient, it minimizes power consumption while maintaining high-performance standards, making it ideal for portable and battery-powered devices. LTE Lite's advanced features ensure it remains a versatile and future-proof choice for next-generation cellular networks, supporting robust communication infrastructures in evolving markets.
In smartphone applications, ActLight’s Dynamic PhotoDetector (DPD) offers a step-change in photodetection technology, enhancing features such as proximity sensing and ambient light detection. This high sensitivity sensor, with its ability to detect subtle changes in light, supports functions like automatic screen brightness adjustments and energy-efficient proximity sensing. Designed for low voltage operation, the DPD effectively reduces power consumption, making it suitable for high-performance phones without increasing thermal load. The technology also facilitates innovative applications like 3D imaging and eye-tracking, adding richness to user experiences in gaming and augmented reality.
The Yuzhen 600 RFID Chip is engineered to provide exceptional performance in RFID applications, utilizing advanced technologies to enable efficient and accurate data capture and processing. This chip is designed for high-speed operations, ensuring that it can handle large volumes of RFID interactions seamlessly. With its robust architecture, the Yuzhen 600 is tailored for use in various environments, from supply chain management to secure access systems, delivering consistent and reliable performance. Its low power consumption and enhanced processing capabilities make it a valuable asset in optimizing RFID systems for better data management and operational efficiency.
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