All IPs > Wireline Communication > Fibre Channel
Fibre Channel semiconductor IPs are crucial components in the infrastructure of high-speed data transfer systems tailored to enterprise storage networking. Known for their reliability and high performance, these semiconductor IPs enable efficient data communication essential for critical data center environments. Fibre Channel technology is a key driver in maintaining seamless connectivity and data flow across enterprise storage networks, ensuring that shared storage resources are accessible, robust, and efficient.
In the realm of wireline communication, Fibre Channel is often chosen for its ability to handle substantial amounts of data traffic with low latency, making it an indispensable technology in settings that require rapid storage and retrieval of information. This technology significantly boosts data handling capabilities and is particularly efficient in managing complex storage area networks (SANs). Moreover, the inherent scalability of Fibre Channel IPs offers enterprises the flexibility to expand and adapt their storage solutions as their data management needs evolve.
Products in this category of semiconductor IP range from basic cores designed for integration into larger system solutions to more advanced IP modules that provide comprehensive functionalities necessary for Fibre Channel implementation. These may include transceiver modules, protocol engines, and physical layer interfaces, all meticulously designed to adhere to industry standards and interoperability requirements. By using Fibre Channel IPs, developers can ensure that their products support high-speed data processing, offering an edge in competitive markets where performance and reliability are paramount.
The adoption of Fibre Channel semiconductor IPs in enterprise networks translates into higher efficiency and enhanced capability to support applications that require substantial bandwidth, such as virtualization and large transactional databases. As data demands continue to grow, leveraging Fibre Channel technology becomes even more critical in the strategic planning of network and storage architecture, providing foundational support for future technological advancements in data management systems.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The EW6181 is an advanced multi-GNSS silicon solution designed for high sensitivity and precision. This powerful chip supports GPS, Glonass, BeiDou, Galileo, SBAS, and A-GNSS, offering integration flexibility with various applications. Its built-in RF frontend and digital baseband facilitate robust signal processing, controlled by an ARM MCU. The EW6181 integrates essential interfaces for diverse connectivity, matched with DC-DC converters and LDOs to minimize BOM in battery-driven setups. This silicon marries low power demands with strong functional capabilities, thanks to proprietary algorithms that optimize its operation. It’s engineered to deliver exceptional accuracy and sensitivity in both standalone and cloud-related environments, adapting smoothly to connected ecosystems for enhanced efficiency. Its compact silicon footprint further enhances its suitability for applications needing prolonged battery life and reliable positioning. With a focus on Antenna Diversity, the EW6181 shines in dynamic applications like action cameras and smartwatches, ensuring clear signal reception even when devices rapidly rotate. This aspect accentuates the chip's ability to maintain consistent performance across a range of challenging environments, reinforcing its role in the forefront of GNSS technology.
The iCan PicoPop® is a highly compact System on Module (SOM) based on the Zynq UltraScale+ MPSoC from Xilinx, suited for high-performance embedded applications in aerospace. Known for its advanced signal processing capabilities, it is particularly effective in video processing contexts, offering efficient data handling and throughput. Its compact size and performance make it ideal for integration into sophisticated systems where space and performance are critical.
SMPTE ST 2110 is a sophisticated protocol designed to facilitate the transport of media over IP networks, commonly used in broadcast and professional AV settings. This IP solution enhances the ability to transmit a variety of media types such as video, audio, and ancillary data via IP, leveraging the modularity to achieve optimal resource efficiency. Supporting an array of sub-standards, including uncompressed video (ST 2110-20) and compressed video (ST 2110-22), this IP bolsters transmission quality and reliability, ensuring consistent system timing and seamless traffic shaping. With its robust support for both gateway and synthetic essence operations, SMPTE ST 2110 enables effective integration with legacy systems and ensures a future-ready setup for the transmission of high-quality media content over IP. The core is highly configurable, allowing users to tailor features according to specific broadcast requirements while maintaining resource efficiency. By utilizing only necessary RTL logic, it minimizes overhead while offering a versatile solution for both professional AV equipment and broadcast systems. Integrated into an ecosystem of proven interoperable standards, this IP ensures smooth transitions between digital and traditional workflows, establishing itself as a pivotal component in AV-over-IP infrastructures. The design includes capabilities to handle various media types, making it adaptable to different operational needs. Nextera’s SMPTE ST 2110 IP is supported by a comprehensive reference design project, inclusive of necessary drivers and control software, enabling rapid system prototyping and deployment. Customers benefit from a well-documented setup that fosters swift development cycles and reduces time-to-market, underpinned by Nextera's emphasis on sustained performance and innovation within IP media experiences.
StreamDSP's MIPI Video Processing Pipeline is crafted for seamless integration into advanced embedded systems, offering a turnkey solution for video handling and processing. It supports the MIPI CSI-2 and DSI-2 standards, allowing it to process various video formats and resolutions efficiently, including ultra-high-definition video. The architecture is designed to work with or without frame buffering, depending on latency needs, enabling system designers to tailor performance to specific application requirements. This flexibility ensures that StreamDSP's video pipeline can handle the demands of cutting-edge video applications like real-time video analysis and broadcast video streaming, while maintaining optimal resource usage.
The CTAccel Image Processor for Intel PAC is crafted to elevate the processing capabilities of data centers by transferring intensive image processing tasks from CPU to FPGA. By exploiting the strengths of Intel's Programmable Acceleration Card (PAC), this IP offers substantial improvements in throughput, latency, and Total Cost of Ownership (TCO). This IP enhances data center efficiency with increased image processing speeds ranging from four to fivefold over traditional CPU solutions, alongside reduced latency by two to threefold. The result is fewer servers needed, translating into lower maintenance and energy costs. Its compatibility with well-known image processing tools ensures that users need not alter their existing setups substantially to benefit from the acceleration offered by the FPGA. Moreover, the CTAccel Image Processor leverages advanced FPGA partial reconfiguration, allowing users to update and adjust computational cores remotely, maximizing performance for specific applications without downtime. This flexibility is pivotal for scenarios involving varied processing loads or evolving computational demands, ensuring uninterrupted performance enhancement.
InnoSilicon's 56G SerDes Solution caters to the high-speed data transfer needs of today's semiconductor industry, offering a robust and flexible platform for a variety of high-bandwidth applications. This SerDes solution provides a comprehensive interface for seamless integration in networking and communication systems, including PCIe, USB, and Ethernet. Engineered for performance, the 56G SerDes boasts multi-protocol support, which allows for versatility in system design. It offers unmatched signal integrity, optimizing data rate speeds across various environments while minimizing electromagnetic interference. This ensures reliable communication channels capable of handling the complexities of modern digital data transfer. The solution's adaptability to different process nodes enhances its utility in diverse technological settings, promoting efficiency and reducing power consumption. It is especially suited for use in data centers, telecommunications infrastructure, and other areas where high-speed data processing is required. Through its advanced modulation techniques and streamlined architecture, the 56G SerDes Solution provides a valuable foundation for building next-generation networking solutions.
ARDSoC is a pioneering embedded DPDK solution tailored for ARM-based SoCs, specifically engineered to enhance ARM processor performance by bypassing the traditional Linux network stack. This solution brings the efficiencies of DPDK, traditionally reserved for datacenter environments, into the embedded and MPSoC sphere, extending DPDK functionalities to a broader range of applications. The architecture of ARDSoC allows users to minimize power consumption, decrease latency, and reduce the total cost of ownership compared to conventional x86 solutions. This IP product facilitates packet processing applications and supports various technologies such as VPP, Docker, and Kubernetes, ensuring hardware-accelerated embedded network processing. Designed for integration across Xilinx Platforms, ARDSoC also offers high flexibility with the ability to run existing DPDK programs with minimal modification. It is optimized for performance on ARM A53 and A72 processors, ensuring that data structures are efficiently produced and consumed in hardware, thereby providing robust and reliable network data handling capabilities.
The INAP375R Receiver is a component of the APIX2 technology suite, tailored to meet the stringent demands of automotive infotainment systems. It supports bi-directional, high-speed data transfer over a single twisted pair cable, up to distances of 12 meters, offering flexibility for complex vehicle architectures. The receiver integrates advanced error correction protocols and supports RGB and LVDS video interfaces, making it ideal for high-definition display applications in vehicles.
Ethernet solutions are a suite of sophisticated design and verification IPs tailored for high-speed networking applications. They are continuously enhanced to comply with the latest specifications while ensuring compatibility with previous standards.\n\nThese solutions encompass a wide range of Ethernet MAC, PCS, and switch components, supporting speeds from 1G to 800G. They are strategically built to manage various data transfer requirements, providing robust performance across networks of different capacities and infrastructures. Additionally, support for AFDX, CPRI, and eCPRI controllers widens the scope for telecommunications and aerospace applications.\n\nPRSemicon's Ethernet IPs are critical for building efficient, high-speed networks that provide the backbone for modern communication systems. Their comprehensive support and adaptability make them a preferred choice in ensuring resilient and reliable connectivity across numerous platforms.
Certus Semiconductor's RF/Analog solutions encompass state-of-the-art ultra-low power wireless front-end technologies. These include silicon-proven RF IPs, full-chip RF products, and next-generation wireless IPs. The RF IPs are compatible with various process nodes, offering comprehensive transceiver solutions integrated with digital controls and modern power management strategies. Specialized for wireless applications, these products include transceivers for LTE, Wifi, GNSS, and Zigbee, each meticulously designed to enhance communication reliability and efficiency in any technology node, from 12nm to 65nm processes.
The APIX3 Transmitter and Receiver Modules represent the pinnacle of automotive data communication, offering superior bandwidth and versatility for in-car network architectures. Capable of handling up to 12Gbps with quad twisted pair connections, APIX3 supports Ultra High Definition video resolutions across multiple channels concurrently. These modules also feature robust diagnostic and cable monitoring capabilities, ensuring uninterrupted operation and ease of maintenance in automotive environments.
The INAP590T is a transmitter module embedded within the APIX3 framework, delivering unparalleled data transfer capabilities for high-resolution automotive display systems. It supports HDMI 1.4a video interface and integrates seamlessly with existing in-car networks. This module offers advanced features such as scalable bandwidth, cable adaptability, and error correction, making it a reliable choice for next-generation infotainment architectures.
The Ethernet 10/100 MAC is engineered to enable efficient communication in networked environments. It provides a flexible and robust interface for baseband Ethernet communication, supporting both 10 Mbps and 100 Mbps data transfer rates. This module integrates essential features needed for seamless networking, including frame handling, error checking, and collision detection, making it adaptable for various networking applications. The solution enhances network reliability and speed, which are crucial for a wide array of industries. Its architecture is designed to optimize performance while ensuring data integrity, crucial for maintaining high-speed operations in complex network configurations. The Ethernet 10/100 MAC is a versatile component, suitable for use in consumer electronics, industrial systems, and other sectors demanding robust network communication support. Its adaptability to different hardware setups makes it an ideal choice for manufacturers looking to implement efficient network solutions across multiple device categories. Furthermore, the modular design allows for easy integration into existing systems, ensuring minimal latency and high throughput. This makes the Ethernet 10/100 MAC a critical component in the development of systems that require reliable network interfacing and effective data exchange across varied environments.
The INAP375T Transmitter is a high-speed data transmission solution specifically designed for the automotive industry. It employs the second generation APIX2 technology, which delivers high-speed differential data through a single twisted pair cable, supporting data rates up to 3Gbps. This transmitter can handle complex multimedia data like video and audio while maintaining robust error correction through the AShell protocol, ensuring reliable data communication within vehicles.
The Akeana 1000 Series is a versatile line of 64-bit RISC-V processors, offering significant configurability for data-intensive and high-performance applications. This midrange series provides support for multi-threading and both in-order and out-of-order microarchitectures, tailored to various industry needs from smart devices to automotive systems. Its comprehensive feature set allows for efficient operation with rich operating systems, such as Linux or Android, providing reliable computing power in diverse environments. With capabilities for scalable processing via a configurable issue width, the Akeana 1000 Series is ideal for edge AI, industrial automation, and advanced automotive applications, where high throughput and precision are crucial. Its architecture allows for flexible configuration of pipeline stages and memory management units, ensuring compatibility with a wide range of computation demands. This processor line offers built-in ECC support, ensuring data integrity in complex computational environments. The series' adaptability is further reinforced by support for physical memory protection, vector extensions, and hypervising capabilities, making it a comprehensive choice for mid-tier processing needs in modern technological ecosystems.
The RT125 is a high-speed device capable of delivering 28Gbps, ideal for short-reach (SR) applications. It combines clock data recovery (CDR), limiting amplifier (LA), and trans-impedance amplifier (TIA) functionalities in a single compact package. Optimized for optical communication infrastructure, the RT125 is built to ensure minimal signal loss and maximum data integrity over short distances. This makes it suitable for modern data center applications where efficient, high-speed data interchange is critical.
The Binary-PSK Demodulator from Zipcores is expertly engineered to handle binary phase shift keying signals, crucial for effective digital communication systems. This core performs demodulation by differentiating between two distinct phases of reference signals, converting the received signals effectively into a data stream. Its design supports reliable interpretation in various unpredictable channels, making it suitable for numerous telecom applications. A standout feature is its ability to balance computational efficiency with processing power, enabling deployment in devices with limited resources while still maintaining high accuracy. Additionally, this demodulator can be integrated seamlessly with existing digital signal processing setups, supporting a wide variety of sample rates and signal frequencies. The compact design and robustness make it ideal for mobile communication systems where power efficiency and signal precision are critical. Furthermore, it ensures compatibility with various hardware platforms, facilitating easy adaptation into both FPGA and ASIC designs.
ERA™ RF Monitoring offers a sophisticated RF spectrum analysis solution, designed to facilitate continuous real-time monitoring of RF environments. It operates efficiently across a wide frequency range, ensuring users gain deep insights into RF activities for enhanced situational awareness. This monitoring system is crucial for maintaining oversight of spectrum usage and detecting unauthorized transmissions, which is vital in sensitive and secure environments. ERA represents Epiq Solutions' commitment to providing top-tier technological support for RF spectrum management, ensuring operations are conducted with the utmost precision and reliability. This innovative system is an essential tool for entities that require strong RF surveillance capabilities, encompassing defense, security, and strategic communication sectors.
KMX 10G MAC and PCS core, which includes media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard. The core supports RS FEC defined in IEEE 802.3 Clause 108 with independent bit error detection and bit error correction. It connects to user logic via AXI4-Stream interface of 64 bits at 156.25MHZ and to 10G PCS core via XGMII interface of 64 bits at 156.25 MHZ. It also connects to user logic via AXI4-Lite interface. The MAC core accepts packets from user logic and generates new format packets by adding Preamble/SFD; padding zero bytes for short packets to 64 bytes; generating 32 bit CRC and padding it. It receives packets from 10G PCS via XGMII interface and generates new format packet by removing Preamble/SFD and 32 bit CRC after CRC checking. It supports Pause Frame processing for flow control and Implements Deficit Idle Count algorithm to ensure maximum possible throughput at the transmit interface. It implements internal XGMII loopback for debug purpose, which at the XGMII interface, the data flow on TX path is redirected to RX path and no data is forwarded to XGMII TX interface. It implements configuration, control, status, statistical information collection and it supports VLAN tagged frame defined IEEE 802.1Q. KMX 10G PCS module connects to 10G MAC module via XGMII of 64 bits at 156.25MHZ and connects to transceiver interface at 64 bits at 161.1328125MHZ. The PCS core is compliant with IEEE 802.3ba specifications. The core supports the following features: It implements 64b/66b encoding/decoding. The core supports 10G scrambling/descrambling of polynomial 1 + x^39 + x^58. It implements gearbox on both TX and RX. The 66-bit block synchronization algorithm implementation is included. The BIP-8 generation/insertion on TX and checking on RX are supported. It implements Bit Error Rate (BER) for monitoring excessive error ratio. The transceiver interface loopback for debug purpose is implemented, which at transceiver interface, the data flow on TX path is redirected to the RX path and no data is forwarded to transceiver TX interface. The core supports link signaling protocol.
A Channelizer is an essential component used in modern communication systems to separate a wide frequency band into multiple narrower sub-bands, allowing for the efficient processing and analysis of complex signal environments. This technology is particularly crucial in applications like satellite communications and broadcasting, where multiple signals are multiplexed over a single channel. The core function of a Channelizer is to maximize bandwidth efficiency while maintaining outstanding signal quality. By dissectively filtering signals, it facilitates the isolation and analysis of individual channels, enabling precise monitoring and control. This not only enhances the overall system's throughput but also supports a cleaner and more organized signal processing architecture. Incorporating Channelizer technology into communication systems ensures robust performance and reliable operation across various signal bands. This provides an adaptable and efficient solution to managing complex communication tasks, especially in environments where both broad and narrow bandwidths are utilized simultaneously.
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