In the semiconductor industry, continuous innovation and collaboration drive the development of cutting-edge technologies. An exciting new development is the launch of Global Unichip Corp.'s (GUC) next-generation 2.5D/3D Advanced Package Technology (APT) platform. This platform, leveraging Taiwan Semiconductor Manufacturing Company’s (TSMC) 3DFabric® and advanced process technologies, promises to accelerate ASIC design cycles and reduce development risks.

A New Era for ASIC Design

GUC's new platform represents a significant leap forward from its first-generation APT platform. It integrates the most recent advancements from TSMC, including their transition from FinFET-based N5/N3 nodes to the novel nanosheet nodes like N2 and A16. This transition has enabled unprecedented integration density, which is crucial for applications in AI, high-performance computing (HPC), and network technology.

Notably, the platform supports HBM4 memory interfaces that double the I/O to 2,048 pins, thereby allowing for significantly higher bandwidth, which is critical for data-intensive applications. For more on the specifics of this advancement, check out Digitimes' in-depth coverage.

Integration with TSMC 3DFabric

TSMC's 3DFabric innovations, such as Chip-on-Wafer-on-Substrate (CoWoS®), System-On-Wafer (SoW™), and TSMC-SoIC®, play a central role in the new APT platform. These technologies allow for the integration of multiple dies on larger package substrates, accommodating more functionality and enhancing performance.

Through deep collaboration with TSMC, GUC has developed silicon-proven intellectual property (IP) that consistently aligns with TSMC's evolving process and packaging innovations. This partnership ensures that GUC's clients benefit from reduced design risk and accelerated product development timelines.

Industry-Leading Innovations

One of GUC’s prominent achievements with this platform is the development of HBM4 PHY IP on TSMC’s N3P process, achieving impressive speeds of 12 Gbps. Furthermore, the GUC’s UCIe Die-to-Die IP, currently offered in TSMC’s N3 and N5 processes, is a testament to their commitment to pushing boundaries. The forthcoming 64G version, scheduled for a late-2025 tape-out, exemplifies future potential.

Additionally, the platform supports GLink/UCIe-3D IP, which boasts phenomenal bandwidth capabilities of 50 Tbps/mm², providing capabilities that are critical for next-generation AI and HPC applications.

The Future of 3D ASICs

GUC’s forward-thinking approach marks the dawn of true 3D ASICs. Their new platform combines cutting-edge IP with TSMC-certified design flows and a wealth of high-volume production experience, offering rapid, low-risk development solutions for next-gen chips.

This platform allows for the integration of advanced process technologies, packaging solutions, and silicon-proven IP, which is vital for customers looking to quickly innovate and bring products to market. To learn more about GUC's comprehensive capabilities, read their press release.

Conclusion

The launch of GUC's next-generation 2.5D/3D APT platform is a game-changing development in the world of semiconductor technology, providing new opportunities for innovation and growth in AI and HPC fields. With TSMC’s collaboration, GUC continues to push the envelope of what is possible, offering comprehensive solutions that meet the evolving needs of the semiconductor industry. This is a fascinating time for the field, as these advancements set the stage for future breakthroughs in technology and design.