Chip Talk > Pioneering the Future: Soitec and PSMC Revolutionize 3D Chip Stacking
Published June 03, 2025
In a thrilling new development for the semiconductor industry, French materials specialist Soitec and Taiwan's semiconductor manufacturing titan PSMC have teamed up to explore new frontiers in 3D chip stacking technology. This partnership represents a significant leap forward in the integration of semiconductor technologies, with the potential to drastically change the landscape of computing architecture.
At the heart of this collaboration is Soitec's Transistor Layer Transfer (TLT) technology. TLT, which has only recently been publicly introduced, is a sophisticated method for transferring ultra-thin transistor layers onto diverse types of wafers. This innovation is a cornerstone for achieving heterogeneous integration — a process essential for developing more efficient semiconductor devices.
Soitec's TLT technology hinges on their proprietary Smart Cut process. This process is remarkable for its ability to function like an atomic-scale scalpel, transferring a thin crystalline layer, ranging from 5 nm to 1 µm, from a donor substrate onto another. This allows active structures to be generated independent of the mechanical substrate, facilitating a wider array of applications that includes but is not limited to, advanced AI systems, autonomous driving technologies, and more.
PSMC's role in this partnership is equally pivotal. Over the past two years, the Taiwan-based firm has been focusing on demonstrating their innovative wafer-stack integrated process. This process leverages Soitec’s substrate technology, broadening the application of 3D technology from just chip-level stacking to transistor-level stacking as well.
This advancement is crucial for overcoming certain limitations traditionally imposed by Moore's Law, allowing for greater miniaturization and increased power efficiency in semiconductor devices. The transition from micrometer to nanometer scales in wafer thickness is a testament to the groundbreaking potential of these technologies.
The applications of these advancements in 3D stacking technology are far-reaching. With the capability to enhance power performance in computing architectures, this collaboration is expected to make significant strides in sectors relying on compact and efficient computing solutions.
From consumer electronics like smartphones and tablets to more complex systems like AI-controlled devices and autonomous vehicles, the integration of these technologies offers immense possibilities. For instance, ultra-fast data processing and reduced power consumption can considerably improve user experience and device capabilities.
As the semiconductor industry continues its rapid evolution, innovations like those coming from the Soitec and PSMC collaboration underscore a broader trend toward increased customization and integration in chip design. The emphasis on heterogeneous integration signifies the industry's shift towards more personalized and efficient hardware solutions that can cater to the specific needs of diverse applications.
Moreover, this collaboration not only represents a technological leap but also sets the stage for future partnerships between substrate innovators and foundries worldwide. By laying the groundwork for more advanced semiconductor designs, Soitec and PSMC are contributing to a domino effect that is likely to inspire similar collaborations across the globe.
The partnership between Soitec and PSMC is more than just a business agreement; it is a testament to the relentless pursuit of innovation in the semiconductor industry. As these two companies work to push the boundaries of what is possible with 3D stacking technology, they are paving the way for a new era of semiconductor capabilities.
For further information about this groundbreaking collaboration, you can read more about it here. This is just the beginning, and the industry will undoubtedly be watching closely as Soitec and PSMC continue to change the face of semiconductor technology.
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