The latest iteration of Cadence's Virtuoso Studio, IC23.1 ISR16, is now available, packed with updates and improvements that promise to enhance the capabilities of electronic design automation.

Overview of Key Updates

The new Virtuoso Studio IC23.1 ISR16 continues to bolster designers' toolkits with a range of enhancements and novel features designed to streamline processes and maintain accuracy in complex designs. Exciting updates in this version include enhanced model file migration, flexible plot type specification options, and more robust support for new symbols.

• Updating Model Files in Schematic Migration
  The latest release has introduced a highly-requested feature that simplifies the schematic migration process. Now, when transitioning a Virtuoso design from one technology file to another, users can update target model files in the migrated maestro views. This is facilitated by a new model mapping file, specifying which sections in the source model correlate with sections in the target model. This improvement is a boon for those involved in intricate design migrations.

• Choosing Plot Types for Outputs
  In a significant user experience enhancement, IC23.1 ISR16 allows designers to pre-select plot types for outputs right within the Outputs Setup tab before any simulation is run. This capability is available in the Virtuoso ADE Explorer and Assembler, making it easier for users to visualize their designs and anticipate outcomes in a more intuitive manner.

• New VPWLFM Symbol
  Another notable highlight includes the addition of a new symbol to the analog library, the vpwlfm. This independent piece-wise linear voltage source based on files for multiple signals expands the flexibility for analog and mixed-signal design. Its incorporation across various components of Virtuoso, such as the ADE Explorer and Schematic Editor, underscores Cadence's commitment to advancing analog simulation capabilities.

• Corner-Specific DCMismatch Summaries
  The ability to view DCmatch mismatch summaries in a tabular format through the Dcmatch summary report window is an added feature in ADE Explorer and Assembler. This update offers greater insight into corner-specific mismatches, enhancing analysis precision and providing designers with crucial data for informed decision-making.

Enhanced RF Solution Capabilities

Additionally, the Virtuoso RF Solution sees improvements with the inclusion of options to specify multi-PDK environment settings. Users can now load settings from multiple text files, providing more flexibility and customization in RF design environments.

Subscribing to Updates and Further Reading

For continuous updates and to dive deeper into these enhancements, designers can explore additional resources such as the "What's New in Virtuoso Studio IC23.1 ISR16" Application Notes and access the "Virtuoso Studio IC23.1 ISR Library." As always, Cadence encourages feedback and questions, offering a direct line through their virtuoso_rm@cadence.com email.

For designers entrenched in semiconductor IP, these updates signal significant advancements in orchestrating complex design tasks efficiently and effectively. Staying abreast of such changes is pivotal, ensuring that your team leverages the latest in technology to maintain a competitive edge.

For more detailed insights into these updates, visit the Cadence Community Blog on Virtuoso.