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The Intelligent Sensor and Power Management Platform (ISP) by IQonIC Works is engineered for sensor-driven and IoT applications that demand refined power management and efficient processing. This platform-centric solution aims to accelerate the design lifecycle, offering an integrated suite of pre-validated IP and design blocks that minimize time-to-market and development costs. ISP focuses on three core design challenges: power management, sensor interface, and software-programmable processing. It provides a comprehensive energy management framework supporting a variety of operational modes, from ultra-low power to active processing states. The platform's capability extends to harvesting and managing energy effectively, which is crucial for battery-operated or energy-scarce environments. The platform's versatility allows for scalable solutions, supporting a wide array of I/O components and processing cores such as RISC-V and ARM Cortex-M variants. It facilitates seamless expansion through industry-standard interfaces, allowing the integration of third-party components and enabling sophisticated communication and control features, ensuring adaptability and robustness in dynamically changing application environments.
The RV32EC_P2 processor core by IQonIC Works is a compact RISC-V processor designed for low-power embedded applications. It features a two-stage pipeline architecture ideal for running trusted firmware and offers a base RV32E instruction set. To enhance efficiency, the core supports RVC compressed instructions for reduced code sizes and optionally includes integer multiplication and division functionalities through the 'M' standard extension. Additionally, it accommodates custom instruction set extensions for tasks such as DSP operations, making it versatile for numerous applications. Designed for ASIC and FPGA implementations, the core provides interfaces like AHB-Lite or APB for memory and I/O operations, ensuring comprehensive system integration. Key features include a simple privileged architecture for machine-mode operations and clock gating for reduced power consumption during idle states. Furthermore, the core supports vectorized interrupts, enabling fast responses to system signals. The RV32EC_P2 is backed by a full suite of development and simulation tools, including synthesis scripts and firmware development environments based on the GNU tool chain. The Virtual Lab (VLAB) system-level tools offer enhanced support for developing and testing applications in a virtual context, ensuring a seamless development experience from conception to deployment.
IQonIC Works' RV32IC_P5 processor core is a high-performance RISC-V solution designed for medium-scale embedded systems requiring advanced processing capabilities and efficient multitasking. Its five-stage pipeline architecture supports complex operations with high-speed processing, catering to applications involving both trusted firmware and user code execution. The core is capable of handling a variety of tasks efficiently due to features like cache memories and privileged machine- and user-modes. This core offers a comprehensive RISC-V RV32I base instruction set and includes optional standard extensions for integer operations (M), user-mode execution (N), and critical section handling (A). It's designed to optimize branch prediction and interrupt response times with configurable buffers and vectorized handling capabilities, which are critical for high-performance applications. Supporting both ASIC and FPGA design flows, the RV32IC_P5 core integrates tightly with memory and I/O interfaces, using AHB-Lite buses for extensive connectivity. The accompanying development environment includes the GNU tool chain and ASTC's VLAB for prototyping and firmware testing, ensuring developers have robust tools for seamless application development and deployment.
IQonIC Works' RISC-V PLIC is designed to handle complex interrupt management tasks in systems with multiple interrupt sources and destinations. Conforming to the RISC-V PLIC specification, the controller is highly configurable to suit the specific needs of various applications. It supports from 31 to 1023 interrupt sources and can manage up to 32 hardware thread (hart) contexts, enabling flexible and efficient interrupt handling across wide-ranging system architectures. The PLIC ensures secure and efficient allocation of interrupts through configurable priority levels and supports asynchronous and synchronous signal requests, as well as edge-triggered sensitivities. Its interface uses AHB-Lite for priority, enables, and claim completion settings, facilitating streamlined processing and response management. Designed for integration into both single and multiprocessor environments, the PLIC allows interrupt sharing across different processor execution contexts, thereby optimizing resource utilization. Through this functionality, the PLIC enhances the system's ability to manage a broad spectrum of asynchronous events, vital for high-performance and real-time applications.
The RISC-V Timer IP from IQonIC Works is tailored to provide efficient timing operations in accordance with RISC-V standards for embedded systems. It offers multiple timer configurations to accommodate the precise needs of various applications, ranging from high-frequency, processor clock-based timing to alternatives that utilize low-power, always-on clocks suitable for energy-constrained environments. With options for both AHB and APB interfaces, the Timer IP can be seamlessly integrated into complex bus architectures or simplified systems, respectively. It supports processor clock cycle counting, which makes it ideal for applications demanding high precision and reliability in timing functions. The timer's versatility is further enhanced by variants that support clock-domain crossing, crucial for power-managed systems where efficiency and modularity are paramount. For developers, the RISC-V Timer IP provides essential deliverables including synthesizable RTL and comprehensive test environments. These are designed to expedite development cycles and ensure the integration process is smooth and efficient, aiding developers in achieving precise timing solutions with minimal overhead.
IQonIC Works offers a versatile USB-C/PD IP, tailored for modern IC and ASIC designs incorporating USB-C/PD functionalities. The IP suite provides both digital and analog design elements necessary for implementing USB Power Delivery features, meeting diverse application needs. With flexible integration options, the USB-C/PD IP supports a broad range of configurations—for sink-only ports, source-only ports, or full dual-role port (DRP) setups. Catering to comprehensive development requirements, the IP suite includes core digital protocols and upper-layer implementations in firmware, complemented by configurable hardware modules. Whether deployed as standalone units or integrated into complex systems, the USB-C/PD solutions are designed for different manufacturing modes, available as soft, hard IP or pre-packaged IC solutions. The USB-C/PD IP ensures high reliability and performance, supported by extensive deliverables such as source code, design guides, and verification environments. It also facilitates diverse manufacturing licenses, adapting to varied project and technology requirements, providing a robust, scalable foundation for advanced power and data transfer capabilities.
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