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The Link Acceleration Unit (LAU) by Panmnesia is a hardware block designed to enhance end-to-end communication over CXL, significantly reducing time-to-market for diverse hardware designs. With device-specific optimizations, the LAU ensures minimal communication latency and deterministic responsiveness, crucial for latency-critical applications. The IP supports hardware-managed cache coherency, eliminating the need for software intervention by automating processes like back invalidation for varying device types. This results in exceptional latency and power efficiency, maximizing performance-per-watt for designs where power savings are critical. Compatible with CXL 3.x and backward compatible with CXL 1.1 and 2.0, the LAU offers comprehensive support for subprotocols such as CXL.io, CXL.mem, and CXL.cache, including P2P communication and dynamic capacity device support. It serves a wide range of CXL device types, making it a versatile solution for AI infrastructure.
The PanRetimer offers high-performance signal regeneration across CXL 3.x and PCIe 6.x links, ensuring data integrity over long distances. It is built using Panmnesia's Link Controller IP and supports ultra-low latency, making it ideal for AI, HPC, and cloud environments. This device maintains excellent signal integrity even in high-density environments, enabling extended connectivity for disaggregated architectures. It is fully compatible with PCIe 6.0 and CXL 3.x, supporting flexible clocking and dynamic polarity to ensure easy adaptability across different systems. Power efficiency is optimized with low-power modes and thermal-aware architecture, aiding in reducing energy consumption. This, combined with its adaptable design, makes the PanRetimer a robust solution for extending the reach of PCIe/CXL connections in complex infrastructures.
PanSwitch is a groundbreaking CXL 3.x switch designed to interconnect a multitude of computing and memory devices within a unified, composable fabric. This switch supports high fan-out architecture and sub-100 nanosecond latency, making it an excellent fit for large-scale AI, HPC, and cloud deployments. The switch features 256 lanes, which allow the connection of numerous GPUs, CPUs, and memory devices, all while maintaining swift and efficient communication. It's the first of its kind to support a full CXL fabric, enhancing network reconfiguration with support for various topology patterns, real-time load balancing, and automated resource optimization. Engineered for minimal latency, the PanSwitch achieves seamless memory expansion with low performance overhead. Its software component includes a fabric manager for configuring, managing, and monitoring the switch, thus ensuring smooth deployment in diverse data center environments.
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